18.5.9 Tamper Control Registers and Detection Logic

The WKUP pins used for fast wake-up in PMC are also routed to the tamper detection logic. Any WKUP pin which is not already configured as source of fast wake-up can be configured and selected as a source of a tamper event.

The tamper event can be used to immediately clear (no peripheral clock required) the content of the GPBR, clear the keys stored in AES/TDES, clear the scrambling keys of QSPI/SDR/DDR/SMC memory controllers. Each of these peripherals embeds a configuration bit to allow/disallow the clear on tamper event.

The polarity of each of the WKUP pins can be configured.

Each of the WKUP pins are debounced prior to create the tamper event.

The tamper event is asserted when one of the lines matches the configured polarity after the debouncing period (see the figure below).

The WKUP pins routed to tamper detection logic are all located on VDDCORE domain, thus there is no tamper detection event when the product is in Backup mode.

To enable WKUPx pin to be a source of tamper event, not already configured for a fast wake-up (refer to PMC configuration), the bit RTC_TMR.ENx must be written to 1.

The polarity of the WKUPx pin is configured in RTC_TMR.POLx.

Two debounce periods can be defined by configuring the fields RTC_TDPR.PERA and RTC_TDPR.PERB.

For each WKPUPx pin, the debounce period can be selected from either RTC_TDPR.PERA or RTC_TDPR.PERB by configuring the bit RTC_TDPR.SELPx.

For safety/security reasons, it is possible to lock the tamper configuration registers by writing RTC_TMR.TLOCK=1. Once written to 1, the only way to clear this bit is to perform a VDDCORE reset.