40.5.1.5 Interrupts

There are 15 interrupt conditions that are detected within the EMAC. These are ORed to make a single interrupt. Depending on the overall system design, this may be passed through a further level of interrupt collection (interrupt controller). On receipt of the interrupt signal, the CPU enters the interrupt handler (Refer to the Interrupt Controller). To ascertain which interrupt has been generated, read the Interrupt Status Register (EMAC_ISR). Note that this register clears itself when read. At reset, all interrupts are disabled.

To enable an interrupt, write to the Interrupt Enable Register (EMAC_IER) with the pertinent interrupt bit set to one.

To disable an interrupt, write to the Interrupt Disable Register (EMAC_IDR) with the pertinent interrupt bit set to one.

To check whether an interrupt is enabled or disabled, read the EMAC_IMR; if the bit is set to one, the interrupt is disabled.