19.7.4 SHDWC Wake-up Inputs Register
| Name: | SHDW_WUIR |
| Offset: | 0x0C |
| Reset: | 0x00000000 |
| Property: | Read/Write |
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR).
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WKUPT0 | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WKUPEN0 | |||||||||
| Access | R | ||||||||
| Reset | 0 |
Bit 16 – WKUPT0 Wake-up 0 Input Type
| Value | Name | Description |
|---|---|---|
| 0 | LOW |
A falling edge followed by a low level on the wake-up 0 input, for a period defined by WKUPDBC, forces wake-up of the core power supply. |
| 1 | HIGH |
A rising edge followed by a high level on the wake-up 0 input, for a period defined by WKUPDBC, forces wake-up of the core power supply. |
Bit 0 – WKUPEN0 Wake-up 0 Input Enable
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE |
The wake-up 0 input has no wake-up effect. |
| 1 | ENABLE |
The wake-up 0 input forces wake-up of the core power supply. |