13.12.8 SCANCON0

Scanner Access Control Register 0

Note:

Setting EN = 0 does not affect any other register content.
Scanner trigger selection can be set using the SCANTRIG register.
This bit can be cleared in software. It is cleared in hardware when LADR > HADR (and a data cycle is not occurring) or when CRCGO = 0.
The CRCEN and CRCGO bits must be set before setting the SGO bit.
See Table 13-2.

Table 13-2. Scanner Operating Modes
TRIGEN	BURSTMD	Scanner Operation
`0`	`0`	Memory access is requested when the CRC module is ready to accept data; the request is granted if no other higher priority source request is pending.
`1`	`0`	Memory access is requested when the CRC module is ready to accept data and trigger selection is true; the request is granted if no other higher priority source request is pending.
`x`	`1`	Memory access is always requested; the request is granted if no other higher priority source request is pending.
Note: Refer to the “System Arbitration” and the “Memory Access Scheme” sections for more details about Priority selection and Memory Access Scheme.

Name:	SCANCON0
Address:	0x360


Bit	7	6	5	4	3	2	1	0
	EN	TRIGEN	SGO			MREG	BURSTMD	BUSY
Access	R/W	R/W	R/W/HC			R/W	R/W	R/W
Reset	0	0	0			1	0	0

Bit 7 – EN Scanner Enable⁽¹⁾

Value	Description
1	Scanner is enabled
0	Scanner is disabled

Bit 6 – TRIGEN Scanner Trigger Enable^(2,5)

Value	Description
1	Scanner trigger is enabled
0	Scanner trigger is disabled

Bit 5 – SGO Scanner GO^(3,4)

Value	Description
1	When the CRC is ready, the Memory region set by the MREG bit will be accessed and data is passed to the CRC peripheral
0	Scanner operations will not occur

Bit 2 – MREG Scanner Memory Region Select⁽²⁾

Value	Description
1	Scanner address points to Data EEPROM
0	Scanner address points to Program Flash Memory

Bit 1 – BURSTMD Scanner Burst Mode⁽⁵⁾

Value	Description
1	Memory access request to the CPU Arbiter is always true
0	Memory access request to the CPU Arbiter is dependent on the CRC request and trigger

Bit 0 – BUSY Scanner Busy Indicator

Value	Description
1	Scanner cycle is in process
0	Scanner cycle is compete (or never started)

Setting EN Scanner Enable(1) = 0 does not affect any other register content. Scanner trigger selection can be set using the SCANTRIG register. This bit can be cleared in software. It is cleared in hardware when LADR > HADR (and a data cycle is not occurring) or when CRCGOCRC Start = 0. The CRCENCRC Enable and CRCGOCRC Start bits must be set before setting the SGO bit. See Table 1. Scanner Operating Modes TRIGEN BURSTMD Scanner Operation 0 0 Memory access is requested when the CRC module is ready to accept data; the request is granted if no other higher priority source request is pending. 1 0 Memory access is requested when the CRC module is ready to accept data and trigger selection is true; the request is granted if no other higher priority source request is pending. x 1 Memory access is always requested; the request is granted if no other higher priority source request is pending. Refer to the “System Arbitration” and the “Memory Access Scheme” sections for more details about Priority selection and Memory Access Scheme.