36.7.11 SPIxINTE

SPI Interrupt Enable Register
Name: SPIxINTE
Address: 0x08B, 0x98

Bit 76543210 
 SRMTIETCZIESOSIEEOSIE RXOIETXUIE  
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 7 – SRMTIE Shift Register Empty Interrupt Enable

ValueDescription
1 Interrupt is enabled
0 Interrupt is not enabled

Bit 6 – TCZIE Transfer Counter is Zero Interrupt Enable

ValueDescription
1 Interrupt is enabled
0 Interrupt is not enabled

Bit 5 – SOSIE Start of Client Select Interrupt Enable

ValueDescription
1 Interrupt is enabled
0 Interrupt is not enabled

Bit 4 – EOSIE End of Client Select Interrupt Enable

ValueDescription
1 Interrupt is enabled
0 Interrupt is not enabled

Bit 2 – RXOIE Receiver Overflow Interrupt Enable

ValueDescription
1 Interrupt is enabled
0 Interrupt is not enabled

Bit 1 – TXUIE Transmitter Underflow Interrupt Enable

ValueDescription
1 Interrupt is enabled
0 Interrupt is not enabled