48.3.2 Supply Current (IDD)(1)

Table 48-2. 
Standard Operating Conditions (unless otherwise stated)
Param. No.Sym.Device CharacteristicsMin.Typ.†Max.UnitsConditions
VDDNote
D100IDDXT4XT = 4 MHz—550770μA3.0V
D100A—450635μA3.0VAll PMD bits are '1'
D101IDDHS8HS = 8 MHz—8801100μA3.0V
D101A—680880μA3.0VAll PMD bits are '1'
D101DIDDHS32HS = 32 MHz—2.83.8mA3.0V
D101E—1.93mA3.0VAll PMD bits are '1'
D102IDDHFO16HFINTOSC = 16 MHz—1.72.5mA3.0V
D102A—1.31.9mA3.0VAll PMD bits are '1'
D103IDDHFO64HFINTOSC = 64 MHz—5.58.2mA3.0V
D103A—3.75.4mA3.0VAll PMD bits are '1'
D104IDDHSPLL64HS+PLL = 64 MHz—5.38mA3.0V
D104A—3.55.3mA3.0VAll PMD bits are '1'
D105IDDIDLEIdle mode, HFINTOSC = 16 MHz—1.251.75mA3.0V
D106IDDDOZE(3)Doze mode, HFINTOSC = 16 MHz, Doze Ratio = 16—1.31.85mA3.0V

† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note:
  1. The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from 
rail-to-rail; all I/O pins are outputs driven low; MCLR = VDD; WDT disabled.
  2. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption.
  3. IDDDOZE = [IDDIDLE*(N-1)/N] + IDDHFO16/N where N = Doze Ratio (see CPUDOZE register).
  4. PMD bits are all in the Default state, no modules are disabled.