23.5.6 Control A

Name: CTRLA
Offset: 0x05
Reset: 0x00
Property: -

Bit 76543210 
 RXCIETXCIEDREIERXSIELBMEABEIERS485[1:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 7 – RXCIE Receive Complete Interrupt Enable

This bit controls whether the Receive Complete Interrupt is enabled or not. When enabled, the interrupt will be triggered when the RXCIF bit in the USARTn.STATUS register is set.
ValueDescription
0 The Receive Complete Interrupt is disabled
1 The Receive Complete Interrupt is enabled

Bit 6 – TXCIE Transmit Complete Interrupt Enable

This bit controls whether the Transmit Complete Interrupt is enabled or not. When enabled, the interrupt will be triggered when the TXCIF bit in the USARTn.STATUS register is set.
ValueDescription
0 The Transmit Complete Interrupt is disabled
1 The Transmit Complete Interrupt is enabled

Bit 5 – DREIE Data Register Empty Interrupt Enable

This bit controls whether the Data Register Empty Interrupt is enabled or not. When enabled, the interrupt will be triggered when the DREIF bit in the USARTn.STATUS register is set.
ValueDescription
0 The Data Register Empty Interrupt is disabled
1 The Data Register Empty Interrupt is enabled

Bit 4 – RXSIE Receiver Start Frame Interrupt Enable

This bit controls whether the Receiver Start Frame Interrupt is enabled or not. When enabled, the interrupt will be triggered when the RXSIF bit in the USARTn.STATUS register is set.
ValueDescription
0 The Receiver Start Frame Interrupt is disabled
1 The Receiver Start Frame Interrupt is enabled

Bit 3 – LBME Loop-Back Mode Enable

This bit controls whether the Loop-back mode is enabled or not. When enabled, an internal connection between the TXD pin and the USART receiver is created, and the input from the RXD pin to the USART receiver is disconnected.
ValueDescription
0 Loop-back mode is disabled
1 Loop-back mode is enabled

Bit 2 – ABEIE Auto-Baud Error Interrupt Enable

This bit controls whether the Auto-baud Error Interrupt is enabled or not. When enabled, the interrupt will be triggered when the ISFIF bit in the USARTn.STATUS register is set.
ValueDescription
0 The Auto-Baud Error Interrupt is disabled
1 The Auto-Baud Error Interrupt is enabled

Bits 1:0 – RS485[1:0] RS-485 Mode

This bit field enables the RS-485 and selects the operation mode. Writing RS485[0] to ‘1’ enables the RS-485 mode, which automatically drives the XDIR pin high one clock cycle before starting transmission and pulls it low again when the transmission is complete. Writing RS485[1] to ‘1’ enables the RS-485 mode, which automatically sets the TXD pin to output one clock cycle before starting transmission and sets it back to input when the transmission is complete.