36.4.2 Obsolete Publication Rev.B - 03/2019

ChapterChanges
Entire Document
  • Added ATmega809/ATmega1609
  • Updated Electrical Characteristics section and Typical Characteristics section
  • Added package drawing for UQFN
  • Updated package drawing for TQFP
Entire Document
  • Editorial updates
Features
  • Added industrial temperature range -40°C to +85°C
Ordering Information
  • Added table of available product numbers
  • Updated Product Information System figure
Entire Document
  • Added support for ATmega808/809/1608/1609
  • Added support for 40-pin PDIP
  • Editorial updates
  • Renamed document type from manual to family data sheet
Features
  • Updated data retention information
  • Extended speed grade information
Memories
  • Added oscillator calibration (OSCCALnnxn) registers
  • SIGROW
    • Updated description to clarify that information is stored in fuse bytes, not in volatile registers.
  • FUSE
    • Clarifying that reserved bits within a fuse byte must be written to ‘0’
    • Removed non-recommended BOD levels in BODCFG
    • Updating access for LOCKBIT from R/W to R
    • Removed misleading reset values
  • Updated Memory Section Access from CPU and UPDI on Locked Device section
AVR_CPU
  • Removed redundant information
CLKCTRL - Clock Controller
  • Added OSC20MCALIBA register
EVSYS - Event System
  • STROBE/STROBEA renamed to STROBEx
  • Event Generators
    • Added Window Compare Match for ADC
    • Updated TCB event generator description
  • Event Users
    • Updated table
  • STROBEn
    • Updated access from R/W to W
  • Updated generator names in CHANNEL
  • Updated table in USER
PORTMUX - Port Multiplexer
  • Added explicit information for EVSYSROUTEA register
BOD - Brown-out Detect
  • Removed non-recommended BOD levels from CTRLB
TCA - 16-bit Timer/Counter Type A
  • Single Slope PWM Generation
    • Revised figure and description
  • Dual Slope PWM
    • Revised figure and description
  • Events
    • Revised description and added table
TCB - 16-bit Timer/Counter Type B
  • Updated block diagram for clock sources
  • Mode figures legend use improved
  • Input Capture Pulse-Width Measurement mode figure corrected
  • 8-bit PWM mode pseudo-code replaced by figure
  • Added output configuration table
RTC - Real-Time Counter
  • Clarified that first PIT interrupt and RTC count tick will be unknown
  • Added Debug Operation section
  • Updated reset values for PER and CMP register
  • Updated access for PITINTFLAGS register
USART - Universal Synchronous and Asynchronous Receiver and Transmitter
  • Structural changes
  • General content improvements
SPI - Serial Peripheral Interface
  • Added INTCTRL register
TWI - Two-Wire Interface
  • Removed misleading internal information from Overview section
  • Cleaned up Dual Control information
  • Clarified APIEN description in SCTRLA
CCL - Configurable Custom Logic
  • Register summary updated: Number n of LUTs and according registers (LUTnCTRLA, LUTnCTRLB, LUTnCTRLC, TRUTHn)
  • Update of terms and descriptions:
    • Block Diagram section
    • CCL Input Selection MUX section
    • Sequencer Logic
    • Events
    • Filter
    • Association LUT-Sequencer
ADC - Analog-to-Digital Converter
  • Updated ADC Timing Diagrams
    • Single Conversion
    • Free-Running Conversion
  • Added information in the Events section
UPDI - Unified Program and Debug Interface
  • General content improvements
  • Updated Access for UROWWRITE in ASI_KEY_STATUS register