10.1.5.3.1 DDR I/O Calibration

The DDR I/Os embed an automatic impedance matching control to avoid overshoots and reach the best performance levels depending on the bus load and external memories. A serial termination connection scheme, where the driver has an output impedance matched to the characteristic impedance of the line, is used to improve signal quality and reduce EMI.

One specific analog input, DDR_CAL, is used to calibrate all DDR I/Os.

The MPDDRC supports the ZQ calibration procedure used to calibrate the SAM9X7 Series DDR I/O drive strength and the commands to set up the external memory device drive strength (refer to DDR-SDRAM Controller (MPDDRC)).

Note: All DDRC pads are calibrated to 50 ohms.

Figure 10-8. DDR Calibration Cell

The calibration cell provides an input pin, DDR_CAL, loaded with the following resistor RZQ value:

20 KΩ ±1% for DDR2 and DDR3L

The CZQ capacitor must not be mounted.

DDR I/Os calibration must be done before initializing the DDR-SDRAM. The calibration is performed by software, via the SFR_CAL1 register. Refer to DDR-SDRAM Controller (MPDDRC) for further details.