4.3.8.4.5 Fast Forcing

The Fast Forcing feature of the advanced interrupt controller provides redirection of any normal Interrupt source on the fast interrupt controller.

Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable register (AIC_FFER) and the Fast Forcing Disable register (AIC_FFDR). Writing to these registers results in an update of the Fast Forcing Status register (AIC_FFSR) that controls the feature for each internal or external interrupt source.

When Fast Forcing is disabled, the interrupt sources are handled as described in the previous sections.

When Fast Forcing is enabled, the edge/level programming and, in certain cases, edge detection of the interrupt source is still active but the source cannot trigger a normal interrupt to the processor and is not seen by the priority handler.

If the interrupt source is programmed in Level-Sensitive mode and an active level is sampled, Fast Forcing results in the assertion of the nFIQ line to the core.

If the interrupt source is programmed in Edge-Triggered mode and an active edge is detected, Fast Forcing results in the assertion of the nFIQ line to the core.

The Fast Forcing feature does not affect the Source 0 pending bit in AIC_IPR.

The FIQ Vector register (AIC_FVR) reads the contents of the Source Vector register (AIC_SVR), whatever the source of the fast interrupt may be. The read of the FVR does not clear Source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to AIC_ICCR.

All enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in Edge-Triggered mode must be cleared by writing to the Interrupt Clear Command register. In doing so, they are cleared independently and thus lost interrupts are prevented.

The read of AIC_IVR does not clear the source that has the fast forcing feature enabled.

Source 0, reserved to the fast interrupt, continues operating normally and becomes one of the Fast Interrupt sources.