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3.6.6.1 DDR-SDRAM Address Mapping for 16-bit Memory Data Bus Width Table 3-20. Sequential Mapping for DDR-SDRAM Configuration, 2K Rows,
256/512/1024/2048/4096 Columns, 4 Banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[10:0] Column[7:0] M0 Bk[1:0] Row[10:0] Column[8:0] M0 Bk[1:0] Row[10:0] Column[9:0] M0 Bk[1:0] Row[10:0] Column[10:0] M0 Bk[1:0] Row[10:0] Column[11:0] M0
Table 3-21. Interleaved Mapping for DDR-SDRAM Configuration, 2K Rows,
256/512/1024/2048/4096 Columns, 4 Banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Row[10:0] Bk[1:0] Column[7:0] M0 Row[10:0] Bk[1:0] Column[8:0] M0 Row[10:0] Bk[1:0] Column[9:0] M0 Row[10:0] Bk[1:0] Column[10:0] M0 Row[10:0] Bk[1:0] Column[11:0] M0
Table 3-22. Sequential Mapping for DDR-SDRAM Configuration: 4K Rows,
256/512/1024/2048/4096 Columns, 4 Banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[11:0] Column[7:0] M0 Bk[1:0] Row[11:0] Column[8:0] M0 Bk[1:0] Row[11:0] Column[9:0] M0 Bk[1:0] Row[11:0] Column[10:0] M0 Bk[1:0] Row[11:0] Column[11:0] M0
Table 3-23. Interleaved Mapping for DDR-SDRAM Configuration: 4K Rows,
256/512/1024/2048/4096 Columns, 4 Banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Row[11:0] Bk[1:0] Column[7:0] M0 Row[11:0] Bk[1:0] Column[8:0] M0 Row[11:0] Bk[1:0] Column[9:0] M0 Row[11:0] Bk[1:0] Column[10:0] M0 Row[11:0] Bk[1:0] Column[11:0] M0
Table 3-24. Sequential Mapping for DDR-SDRAM Configuration: 8K Rows,
512/1024/2048/4096 Columns, 4 Banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[12:0] Column[8:0] M0 Bk[1:0] Row[12:0] Column[9:0] M0 Bk[1:0] Row[12:0] Column[10:0] M0 Bk[1:0] Row[12:0] Column[11:0] M0
Table 3-25. Interleaved Mapping for DDR-SDRAM Configuration: 8K Rows,
512/1024/2048/4096 Columns, 4 Banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Row[12:0] Bk[1:0] Column[8:0] M0 Row[12:0] Bk[1:0] Column[9:0] M0 Row[12:0] Bk[1:0] Column[10:0] M0 Row[12:0] Bk[1:0] Column[11:0] M0
Table 3-26. Sequential Mapping for DDR-SDRAM Configuration: 16K Rows,
512/1024/2048 Columns, 4 Banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[13:0] Column[8:0] M0 Bk[1:0] Row[13:0] Column[9:0] M0 Bk[1:0] Row[13:0] Column[10:0] M0
Table 3-27. Interleaved Mapping for DDR-SDRAM Configuration: 16K Rows,
512/1024/2048 Columns, 4 Banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Row[13:0] Bk[1:0] Column[8:0] M0 Row[13:0] Bk[1:0] Column[9:0] M0 Row[13:0] Bk[1:0] Column[10:0] M0
Table 3-28. Sequential Mapping for DDR-SDRAM Configuration: 8K Rows, 1024
Columns, 8 Banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[2:0] Row[12:0] Column[9:0] M0
Table 3-29. Interleaved Mapping for DDR-SDRAM Configuration: 8K Rows, 1024
Columns, 8 Banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Row[12:0] Bk[2:0] Column[9:0] M0
Table 3-30. Sequential Mapping for DDR-SDRAM Configuration: 16K Rows, 1024
Columns, 8 Banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[2:0] Row[13:0] Column[9:0] M0
Table 3-31. Interleaved Mapping for DDR-SDRAM Configuration: 16K Rows, 1024
Columns, 8 Banks CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Row[13:0] Bk[2:0] Column[9:0] M0
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