5.8.7.14 ISC Interrupt Status Register
| Name: | ISC_INTSR |
| Offset: | 0x34 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| GFOV | CCIRERR | HDTO | VDTO | DAOV | VFPOV | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RERR | WERRID[1:0] | WERR | |||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| HISCLR | HISDONE | LDONE | DDONE | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIS | SWRST | HD | VD | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 29 – GFOV FIFO Overflow Interrupt (relevant if MIPI interface is not selected) (cleared on read)
| Value | Description |
|---|---|
| 0 |
No FIFO overflow detected since the last read of the Interrupt Status register. |
| 1 | A FIFO overflow has been detected. |
Bit 28 – CCIRERR CCIR Decoder Error Interrupt (cleared on read)
| Value | Description |
|---|---|
| 0 | No CCIR CRC error detected since the last read of the Interrupt Status register. |
| 1 | A CCIR CRC error has been detected. |
Bit 27 – HDTO Horizontal Synchronization Timeout Interrupt (cleared on read)
| Value | Description |
|---|---|
| 0 | A horizontal synchronization is detected. |
| 1 | No horizontal synchronization is detected. |
Bit 26 – VDTO Vertical Synchronization Timeout Interrupt (cleared on read)
| Value | Description |
|---|---|
| 0 | A vertical synchronization is detected. |
| 1 | No vertical synchronization is detected. |
Bit 25 – DAOV Data Overflow Interrupt (cleared on read)
| Value | Description |
|---|---|
| 0 | No data overflow error occurred since the last reset of the Interrupt Status register. |
| 1 | A data overflow occurred. |
Bit 24 – VFPOV Vertical Front Porch Overflow Interrupt (cleared on read)
| Value | Description |
|---|---|
| 0 | No vertical front porch error occurred since the last read of the Interrupt Status register. |
| 1 | The vertical synchronization has been detected but the DMA channel is still busy. |
Bit 20 – RERR Read Channel Error Interrupt (cleared on read)
| Value | Description |
|---|---|
| 0 | No read channel error since the last read of the Interrupt Status register. |
| 1 | A read channel error occurred when the ISC read the descriptor. |
Bits 18:17 – WERRID[1:0] Write Channel Error Identifier (cleared on read)
| Value | Name | Description |
|---|---|---|
| 0 | CH0 | An error occurred for Channel 0 (RAW/RGB/Y) |
| 1 | CH1 | An error occurred for Channel 1 (CbCr/Cb) |
| 2 | CH2 | An error occurred for Channel 2 (Cr) |
| 3 | WB | Write back channel error |
Bit 16 – WERR Write Channel Error Interrupt (cleared on read)
| Value | Description |
|---|---|
| 0 | No write channel error since the last read of the Interrupt Status register. |
| 1 | A write channel error occurred. |
Bit 13 – HISCLR Histogram Clear Interrupt (cleared on read)
| Value | Description |
|---|---|
| 0 | No Histogram Clear Interrupt has been raised since the last read of the Interrupt Status register. |
| 1 | The Histogram Clear Interrupt has occurred. |
Bit 12 – HISDONE Histogram Completed Interrupt (cleared on read)
| Value | Description |
|---|---|
| 0 | No Histogram Completed Interrupt has been raised since the last read of the Interrupt Status register. |
| 1 | The Histogram Completed Interrupt has occurred. |
Bit 9 – LDONE DMA List Done Interrupt (cleared on read)
| Value | Description |
|---|---|
| 0 | No DMA List Done interrupt has occurred since the last read of the Interrupt Status register. |
| 1 | The DMA List Done interrupt has occurred. |
Bit 8 – DDONE DMA Done Interrupt (cleared on read)
| Value | Description |
|---|---|
| 0 | No DMA Transfer Done interrupt has occurred since the last read of the Interrupt Status register. |
| 1 | The DMA Transfer Done interrupt has occurred. |
Bit 5 – DIS Disable Completed Interrupt (cleared on read)
| Value | Description |
|---|---|
| 0 | The disable has not occurred since the last read of the Interrupt Status register. |
| 1 | The disable has completed. |
Bit 4 – SWRST Software Reset Completed Interrupt (cleared on read)
| Value | Description |
|---|---|
| 0 | No software reset completion since the last read of the Interrupt Status register. |
| 1 | The software reset has completed. |
Bit 1 – HD Horizontal Synchronization Detected Interrupt (cleared on read)
| Value | Description |
|---|---|
| 0 | No horizontal synchronization detection since the last read of the Interrupt Status register. |
| 1 | A horizontal synchronization has been detected. |
Bit 0 – VD Vertical Synchronization Detected Interrupt (cleared on read)
| Value | Description |
|---|---|
| 0 | No vertical synchronization detection since the last read of the Interrupt Status register. |
| 1 | A vertical synchronization has been detected. |