When a disable request occurs on a suspended channel, the XDMAC_GWS.WSx (Channel x
Write Suspend bit) is cleared. If the transfer is source peripheral synchronized,
the pending bytes are drained to memory. The bit XDMAC_CISx.DIS is set.
When a disable request follows a flush request, if the flush last transaction is not
yet scheduled, the flush request is discarded and the disable procedure is applied.
Bit XDMAC_CISx.FIS is not set. Bit XDMAC_CISx.DIS is set when the disable request is
completed. If the flush request transaction is already scheduled, the XDMAC_CISx.FIS
is set. XDMAC_CISx.DIS is also set when the disable request is completed.
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