8.8.6.2.2 Waveform Properties

The different properties of output waveforms are:

• the internal clock selection. The internal channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. This channel parameter is defined in the CPRE field of the Channel Mode register (PWM_CMRx) This field is reset at 0.
• the waveform period. This channel parameter is defined in the PWM_CPRDx.CPRD field.
  • If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated:

    • By using the peripheral clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:

$\frac{\left(X\times \mathrm{CPRD}\right)}{\mathrm{MCK}}$


    • By using a peripheral clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: 

$\frac{\left(X\text{*}\mathrm{CPRD}\text{*}\mathrm{DIVA}\right)}{\mathrm{MCK}}$ or $\frac{\left(X\text{*}\mathrm{CPRD}\text{*}\mathrm{DIVB}\right)}{\mathrm{MCK}}$
  • If the waveform is center-aligned then the output waveform period depends on the counter source clock and can be calculated:

    • By using the peripheral clock divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:

$\frac{\left(2\times X\times \mathrm{CPRD}\right)}{\mathrm{MCK}}$
    • By using a peripheral clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:

$\frac{\left(2\text{*}X\text{*}\mathrm{CPRD}\text{*}\mathrm{DIVA}\right)}{\mathrm{MCK}}$ or $\frac{\left(2\text{*}X\text{*}\mathrm{CPRD}\text{*}\mathrm{DIVB}\right)}{\mathrm{MCK}}$
• the waveform duty cycle. This channel parameter is defined in the PWM_CDTYx.CDTY field. 
If the waveform is left-aligned, then: 

 $\text{duty cycle}=\frac{\left(\mathrm{PWM\_period}-\mathrm{}(\text{CDTY}\times \mathrm{SRC\_period)}\right)}{\mathrm{PWM\_period}}$

  

If the waveform is center-aligned, then:

$\text{duty cycle}=\frac{\left(\left(\frac{PWM\_period}{2}\right)-\mathrm{}(\text{CDTY}\times \mathrm{SRC\_period}\right))}{\left(\frac{PWM\_period}{2}\right)}$


  where:

  "PWM_period" is the PWM output period and "SRC_period" is the PWM source clock period. "SRC_period" depends on the peripheral clock period and on PWM_CMRx.CPRE, PWM_CLK.(PREA, PREB, DIVA, DIVB), PWM_CPRDx.CPRD and PWM_CMRx.CPRE as per previous formulas.

• the waveform polarity. At the beginning of the period, the signal can be at high or low level. This property is defined in the PWM_CMRx.CPOL field. By default the signal starts by a low level.
• the waveform alignment. The output waveform can be left or center-aligned. Center-aligned waveforms can be used to generate non overlapped waveforms. This property is defined in the PWM_CMRx.CALG field. The default mode is left-aligned.

Note: See the figure below for a detailed description of center-aligned waveforms.

When center-aligned, the internal channel counter increases up to CPRD and decreases down to 0. This ends the period.

When left-aligned, the internal channel counter increases up to CPRD and is reset. This ends the period.

Thus, for the same CPRD value, the period for a center-aligned channel is twice the period for a left-aligned channel.

Waveforms are fixed at 0 when:

• CDTY = CPRD and CPOL = 0
• CDTY = 0 and CPOL = 1

Waveforms are fixed at 1 (once the channel is enabled) when:

• CDTY = 0 and CPOL = 0
• CDTY = CPRD and CPOL = 1

The waveform polarity must be set before enabling the channel. This immediately affects the channel output level. Changes on channel polarity are not taken into account while the channel is enabled.