4.17.9.1 ULP1 Mode

When the system is in Ultra-Low Power 1 (ULP1) mode, all clocks of the system except MD_SLCK are stopped. The source clock of all MCKx must be set to the main clock, and the source of the main clock must be set to main RC oscillator.

Prior to instructing the device to enter ULP1 mode:

1. Select Main RC as the source of MAINCK by configuring CKGR_MOR.MOSCSEL to ‘0’.
2. Select MAINCK as the source of MCK by configuring PMC_CPU_CKR.CSS to ‘1’.
3. Disable the PLL if enabled and disable the main crystal oscillator by setting CKGR_MOR.MOSCXTEN to ‘0’.
4. Wait for two SLCK clock cycles.
5. Clear the internal wake-up sources.
6. Verify that none of the enabled external wake-up inputs (WKUP) hold an active polarity.

The system enters ULP1 mode by setting CKGR_MOR.ULP1. The PMC registers must not be accessed immediately after this access.