8.4.6.7.3 SPI Mode Flow Diagram
The figure below shows Transmit Data Register Empty (TDRE), Receive Data Register Full (RDRF) and Transmission Register Empty (TXEMPTY) status flags behavior within the QSPI_ISR during an 8-bit data transfer, without DMA.
Note: Due to the internal architecture (see Block
Diagram):
- A latency occurs between the TXEMPTY rise and the end of the frame
- A delay occurs between the end of the frame and the RDRF flag rise