3.2.5.4.5 Device (FPGA, Static Memory, etc.) on NCS0, DDR on NCS1 and NAND Flash on NCS2

In this configuration, the device on NCS0, DDR2-SDRAM and NAND Flash are on the same data bus and use the same power supply. As DDR2-SDRAM is used, all components attached to the EBI must be 1.8V powered. NFD0_ON_D16 must be set to 0 in this configuration (NFD0_ON_D16 = 1 is a forbidden configuration with three devices on the EBI). As a few control signals are powered by the VDDNF domain, this configuration forces VDDNF to be powered at 1.8V like VDDIOM. Note this configuration is not supported when using DDR3L-SDRAM.

Figure 3-11. Configuration Example: FPGA on NCS0, DDR on NCS1 and NAND Flash on NCS2

Note: For signal integrity purposes, it is good practice to give priority on the PCB layout to the Processor - DDR2 interface and to isolate this interface from the FPGA and the NAND Flash with serial resistors in the 50 to 200 Ohms range. This configuration implies speed limitation on both the DDR2 interface depending on the layout performance and the device connected to the bus. A signal integrity board simulation must be performed to assess the expected speed operation.