Introduction
Reference Document
1 Overview
2 CPU and Interconnect
3 Memories
4 System Controller
5 Image Subsystem
6 Audio Subsystem
7 Security and Cryptography Subsystem
8 Connectivity Subsystem
- 8.1 Overview
- 8.2 Ethernet MAC (GMAC)
- 8.3 Flexible Serial Communication Controller (FLEXCOM)
  - 8.3.1 Description
  - 8.3.2 Embedded Characteristics
  - 8.3.3 Block Diagram
  - 8.3.4 I/O Lines Description
  - 8.3.5 Product Dependencies
  - 8.3.6 Register Accesses
  - 8.3.7 USART Functional Description
  - 8.3.8 SPI Functional Description
  - 8.3.9 TWI Functional Description
  - 8.3.10 Register Summary
    - 8.3.10.1 FLEXCOM Mode Register
      FLEXCOM Mode Register
    - 8.3.10.2 FLEXCOM Receive Holding Register
      FLEXCOM Receive Holding Register
    - 8.3.10.3 FLEXCOM Transmit Holding Register
      FLEXCOM Transmit Holding Register
    - 8.3.10.4 USART Control Register
      USART Control Register
    - 8.3.10.5 USART Mode Register
      USART Mode Register
    - 8.3.10.6 USART Interrupt Enable Register (Default Mode)
      USART Interrupt Enable Register (Default Mode)
    - 8.3.10.7 USART Interrupt Enable Register (LIN_MODE)
      USART Interrupt Enable Register (LIN_MODE)
    - 8.3.10.8 USART Interrupt Enable Register (LON_MODE)
      USART Interrupt Enable Register (LON_MODE)
    - 8.3.10.9 USART Interrupt Disable Register (Default Mode)
      USART Interrupt Disable Register (Default Mode)
    - 8.3.10.10 USART Interrupt Disable Register (LIN_MODE)
      USART Interrupt Disable Register (LIN_MODE)
    - 8.3.10.11 USART Interrupt Disable Register (LON_MODE)
      USART Interrupt Disable Register (LON_MODE)
    - 8.3.10.12 USART Interrupt Mask Register (Default Mode)
      USART Interrupt Mask Register (Default Mode)
    - 8.3.10.13 USART Interrupt Mask Register (LIN_MODE)
      USART Interrupt Mask Register (LIN_MODE)
    - 8.3.10.14 USART Interrupt Mask Register (LON_MODE)
      USART Interrupt Mask Register (LON_MODE)
    - 8.3.10.15 USART Channel Status Register (Default Mode)
      USART Channel Status Register (Default Mode)
    - 8.3.10.16 USART Channel Status Register (LIN_MODE)
      USART Channel Status Register (LIN_MODE)
    - 8.3.10.17 USART Channel Status Register (LON_MODE)
      USART Channel Status Register (LON_MODE)
    - 8.3.10.18 USART Receive Holding Register (Default Mode)
      USART Receive Holding Register (Default Mode)
    - 8.3.10.19 USART Receive Holding Register (FIFO Multi Data)
      USART Receive Holding Register (FIFO Multi Data)
    - 8.3.10.20 USART Transmit Holding Register (Default Mode)
      USART Transmit Holding Register (Default Mode)
    - 8.3.10.21 USART Transmit Holding Register (FIFO Multi Data)
      USART Transmit Holding Register (FIFO Multi Data)
    - 8.3.10.22 USART Baud Rate Generator Register
      USART Baud Rate Generator Register
    - 8.3.10.23 USART Receiver Timeout Register
      USART Receiver Timeout Register
    - 8.3.10.24 USART Transmitter Timeguard Register
      USART Transmitter Timeguard Register
    - 8.3.10.25 USART Transmitter Timeguard Register (LON_MODE)
      USART Transmitter Timeguard Register (LON_MODE)
    - 8.3.10.26 USART FI DI RATIO Register
      USART FI DI RATIO Register
    - 8.3.10.27 USART FI DI RATIO Register (LON_MODE)
      USART FI DI RATIO Register (LON_MODE)
    - 8.3.10.28 USART Number of Errors Register
      USART Number of Errors Register
    - 8.3.10.29 USART IrDA FILTER Register
      USART IrDA FILTER Register
    - 8.3.10.30 USART Manchester Configuration Register
      USART Manchester Configuration Register
    - 8.3.10.31 USART LIN Mode Register
      USART LIN Mode Register
    - 8.3.10.32 USART LIN Identifier Register
      USART LIN Identifier Register
    - 8.3.10.33 USART LIN Baud Rate Register
      USART LIN Baud Rate Register
    - 8.3.10.34 USART LON Mode Register
      USART LON Mode Register
    - 8.3.10.35 USART LON Preamble Register
      USART LON Preamble Register
    - 8.3.10.36 USART LON Data Length Register
      USART LON Data Length Register
    - 8.3.10.37 USART LON L2HDR Register
      USART LON L2HDR Register
    - 8.3.10.38 USART LON Backlog Register
      USART LON Backlog Register
    - 8.3.10.39 USART LON Beta1 Tx Register
      USART LON Beta1 Tx Register
    - 8.3.10.40 USART LON Beta1 Rx Register
      USART LON Beta1 Rx Register
    - 8.3.10.41 USART LON Priority Register
      USART LON Priority Register
    - 8.3.10.42 USART LON IDT Tx Register
      USART LON IDT Tx Register
    - 8.3.10.43 USART LON IDT Rx Register
      USART LON IDT Rx Register
    - 8.3.10.44 USART IC DIFF Register
      USART IC DIFF Register
    - 8.3.10.45 USART Comparison Register
      USART Comparison Register
    - 8.3.10.46 USART FIFO Mode Register
      USART FIFO Mode Register
    - 8.3.10.47 USART FIFO Level Register
      USART FIFO Level Register
    - 8.3.10.48 USART FIFO Interrupt Enable Register
      USART FIFO Interrupt Enable Register
    - 8.3.10.49 USART FIFO Interrupt Disable Register
      USART FIFO Interrupt Disable Register
    - 8.3.10.50 USART FIFO Interrupt Mask Register
      USART FIFO Interrupt Mask Register
    - 8.3.10.51 USART FIFO Event Status Register
      USART FIFO Event Status Register
    - 8.3.10.52 USART Write Protection Mode Register
      USART Write Protection Mode Register
    - 8.3.10.53 USART Write Protection Status Register
      USART Write Protection Status Register
    - 8.3.10.54 SPI Control Register
      SPI Control Register
    - 8.3.10.55 SPI Mode Register
      SPI Mode Register
    - 8.3.10.56 SPI Receive Data Register (Default Mode)
      SPI Receive Data Register (Default Mode)
    - 8.3.10.57 SPI Receive Data Register (FIFO Multiple Data, 8-bit)
      SPI Receive Data Register (FIFO Multiple Data, 8-bit)
    - 8.3.10.58 SPI Receive Data Register (FIFO Multiple Data, 16-bit)
      SPI Receive Data Register (FIFO Multiple Data, 16-bit)
    - 8.3.10.59 SPI Transmit Data Register
      SPI Transmit Data Register
    - 8.3.10.60 SPI Transmit Data Register (FIFO Multiple Data, 8- to 16-bit)
      SPI Transmit Data Register (FIFO Multiple Data, 8- to 16-bit)
    - 8.3.10.61 SPI Status Register
      SPI Status Register
    - 8.3.10.62 SPI Interrupt Enable Register
      SPI Interrupt Enable Register
    - 8.3.10.63 SPI Interrupt Disable Register
      SPI Interrupt Disable Register
    - 8.3.10.64 SPI Interrupt Mask Register
      SPI Interrupt Mask Register
    - 8.3.10.65 SPI Chip Select Register
      SPI Chip Select Register
    - 8.3.10.66 SPI FIFO Mode Register
      SPI FIFO Mode Register
    - 8.3.10.67 SPI FIFO Level Register
      SPI FIFO Level Register
    - 8.3.10.68 SPI Comparison Register
      SPI Comparison Register
    - 8.3.10.69 SPI CRC Register
      SPI CRC Register
    - 8.3.10.70 SPI Two-Pin Mode Register
      SPI Two-Pin Mode Register
    - 8.3.10.71 SPI Two-Pin Header Register
      SPI Two-Pin Header Register
    - 8.3.10.72 SPI Write Protection Mode Register
      SPI Write Protection Mode Register
    - 8.3.10.73 SPI Write Protection Status Register
      SPI Write Protection Status Register
    - 8.3.10.74 TWI Control Register (Default Mode)
      TWI Control Register (Default Mode)
    - 8.3.10.75 TWI Control Register (FIFO_ENABLED)
      TWI Control Register (FIFO_ENABLED)
    - 8.3.10.76 TWI Host Mode Register
      TWI Host Mode Register
    - 8.3.10.77 TWI Client Mode Register
      TWI Client Mode Register
    - 8.3.10.78 TWI Internal Address Register
      TWI Internal Address Register
    - 8.3.10.79 TWI Clock Waveform Generator Register
      TWI Clock Waveform Generator Register
    - 8.3.10.80 TWI Status Register (Default Mode)
      TWI Status Register (Default Mode)
    - 8.3.10.81 TWI Status Register (FIFO ENABLED)
      TWI Status Register (FIFO ENABLED)
    - 8.3.10.82 TWI Interrupt Enable Register
      TWI Interrupt Enable Register
    - 8.3.10.83 TWI Interrupt Disable Register
      TWI Interrupt Disable Register
    - 8.3.10.84 TWI Interrupt Mask Register
      TWI Interrupt Mask Register
    - 8.3.10.85 TWI Receive Holding Register (Default Mode)
      TWI Receive Holding Register (Default Mode)
    - 8.3.10.86 TWI Receive Holding Register (FIFO Enabled)
      TWI Receive Holding Register (FIFO Enabled)
    - 8.3.10.87 TWI Transmit Holding Register (Default Mode)
      TWI Transmit Holding Register (Default Mode)
    - 8.3.10.88 TWI Transmit Holding Register (FIFO Enabled)
      TWI Transmit Holding Register (FIFO Enabled)
    - 8.3.10.89 TWI SMBus Timing Register
      TWI SMBus Timing Register
    - 8.3.10.90 TWI High-Speed Register
      TWI High-Speed Register
    - 8.3.10.91 TWI Alternative Command Register
      TWI Alternative Command Register
    - 8.3.10.92 TWI Filter Register
      TWI Filter Register
    - 8.3.10.93 TWI High-Speed Clock Waveform Generator Register
      TWI High-Speed Clock Waveform Generator Register
    - 8.3.10.94 TWI FIFO Mode Register
      TWI FIFO Mode Register
    - 8.3.10.95 TWI FIFO Level Register
      TWI FIFO Level Register
    - 8.3.10.96 TWI FIFO Status Register
      TWI FIFO Status Register
    - 8.3.10.97 TWI FIFO Interrupt Enable Register
      TWI FIFO Interrupt Enable Register
    - 8.3.10.98 TWI FIFO Interrupt Disable Register
      TWI FIFO Interrupt Disable Register
    - 8.3.10.99 TWI FIFO Interrupt Mask Register
      TWI FIFO Interrupt Mask Register
    - 8.3.10.100 TWI Write Protection Mode Register
      TWI Write Protection Mode Register
    - 8.3.10.101 TWI Write Protection Status Register
      TWI Write Protection Status Register
- 8.4 Quad Serial Peripheral Interface (QSPI)
- 8.5 Secure Digital MultiMedia Card Controller (SDMMC)
- 8.6 Controller Area Network (MCAN)
- 8.7 Timer Counter (TC)
- 8.8 Pulse Width Modulation Controller (PWM)
9 USB Subsystem
10 Electrical and Mechanical Characteristics
11 Revision History
Microchip Information

8.3.10.5 USART Mode Register

This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.

Name:	FLEX_US_MR
Offset:	0x204
Reset:	0xC0000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	ONEBIT	MODSYNC	MAN	FILTER		MAX_ITERATION[2:0]
Access	R/W	R/W	R/W	R/W		R/W	R/W	R/W
Reset	–	–	–	–		–	–	–


Bit	23	22	21	20	19	18	17	16
	INVDATA	VAR_SYNC	DSNACK	INACK	OVER	CLKO	MODE9	MSBF
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	–	–	–	–	–	–	–	–


Bit	15	14	13	12	11	10	9	8
	CHMODE[1:0]		NBSTOP[1:0]		PAR[2:0]			SYNC
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	–	–	–	–	–	–	–	–


Bit	7	6	5	4	3	2	1	0
	CHRL[1:0]		USCLKS[1:0]		USART_MODE[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	–	–	–	–	–	–	–	–

Bit 31 – ONEBIT Start Frame Delimiter Selector

Value	Description
0	Start frame delimiter is COMMAND or DATA SYNC.
1	Start frame delimiter is one bit.

Bit 30 – MODSYNC Manchester Synchronization Mode

Value	Description
0	The Manchester start bit is a 0 to 1 transition
1	The Manchester start bit is a 1 to 0 transition.

Bit 29 – MAN Manchester Encoder/Decoder Enable

Value	Description
0	Manchester encoder/decoder are disabled.
1	Manchester encoder/decoder are enabled.

Bit 28 – FILTER Receive Line Filter

Value	Description
0	The USART does not filter the receive line.
1	The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).

Bits 26:24 – MAX_ITERATION[2:0] Maximum Number of Automatic Iterations

Value	Description
0–7	Defines the maximum number of iterations in mode ISO7816, protocol T = 0.

Bit 23 – INVDATA Inverted Data

Value	Description
0	The data field transmitted on TXD line is the same as the one written in FLEX_US_THR or the content read in FLEX_US_RHR is the same as RXD line. Normal mode of operation.
1	The data field transmitted on TXD line is inverted (voltage polarity only) compared to the value written in FLEX_US_THR or the content read in FLEX_US_RHR is inverted compared to what is received on RXD line (or ISO7816 IO line). Inverted mode of operation, useful for contactless card application. To be used with configuration bit MSBF.

Bit 22 – VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter

Value	Description
0	User defined configuration of command or data sync field depending on MODSYNC value.
1	The sync field is updated when a character is written into FLEX_US_THR.

Bit 21 – DSNACK Disable Successive NACK

The MAX_ITERATION field must be cleared if DSNACK is cleared.

Value	Description
0	NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
1	Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITER is asserted.

Bit 20 – INACK Inhibit Non Acknowledge

Value	Description
0	The NACK is generated.
1	The NACK is not generated.

Bit 19 – OVER Oversampling Mode

Value	Description
0	16x Oversampling.
1	8x Oversampling.

Bit 18 – CLKO Clock Output Select

Value	Description
0	The USART does not drive the SCK pin (Synchronous Client mode or Asynchronous mode with external baud rate clock source).
1	The USART drives the SCK pin if USCLKS does not select the external clock SCK (USART Synchronous Host mode).

Bit 17 – MODE9 9-bit Character Length

Value	Description
0	CHRL defines character length.
1	9-bit character length.

Bit 16 – MSBF Bit Order

Value	Description
0	Least significant bit is sent/received first.
1	Most significant bit is sent/received first.

Bits 15:14 – CHMODE[1:0] Channel Mode

Value	Name	Description
0	NORMAL	Normal mode
1	AUTOMATIC	Automatic Echo. Receiver input is connected to the TXD pin.
2	LOCAL_LOOPBACK	Local Loopback. Transmitter output is connected to the Receiver Input.
3	REMOTE_LOOPBACK	Remote Loopback. RXD pin is internally connected to the TXD pin.

Bits 13:12 – NBSTOP[1:0] Number of Stop Bits

Value	Name	Description
0	1_BIT	1 stop bit
1	1_5_BIT	1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
2	2_BIT	2 stop bits

Bits 11:9 – PAR[2:0] Parity Type

Value	Name	Description
0	EVEN	Even parity
1	ODD	Odd parity
2	SPACE	Parity forced to 0 (Space)
3	MARK	Parity forced to 1 (Mark)
4	NO	No parity
6	MULTIDROP	Multidrop mode

Bit 8 – SYNC Synchronous Mode Select

Value	Description
0	USART operates in Asynchronous mode (UART).
1	USART operates in Synchronous mode.

Bits 7:6 – CHRL[1:0] Character Length

Value	Name	Description
0	5_BIT	Character length is 5 bits
1	6_BIT	Character length is 6 bits
2	7_BIT	Character length is 7 bits
3	8_BIT	Character length is 8 bits

Bits 5:4 – USCLKS[1:0] Clock Selection

Value	Name	Description
0	MCK	Peripheral clock is selected
1	DIV	Peripheral clock divided (DIV = 8) is selected
2	GCLK	PMC generic clock is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1.
3	SCK	External pin SCK is selected

Bits 3:0 – USART_MODE[3:0] USART Mode of Operation

Values not listed in the table below should be considered ‘reserved’.

Value	Name	Description
0x0	NORMAL	Normal mode
0x1	RS485	RS485
0x2	HW_HANDSHAKING	Hardware handshaking
0x4	IS07816_T_0	IS07816 Protocol: T = 0
0x6	IS07816_T_1	IS07816 Protocol: T = 1
0x8	IRDA	IrDA
0x9	LON	LON
0xA	LIN_MASTER	LIN Host mode
0xB	LIN_SLAVE	LIN Client mode
0xC	DATA16BIT_MASTER	16-bit data host
0xD	DATA16BIT_SLAVE	16-bit data client

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