8.3.10.51 USART FIFO Event Status Register

Name: FLEX_US_FESR
Offset: 0x2B4
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
       RXFTHF2TXFLOCK 
Access RR 
Reset 00 
Bit 76543210 
 RXFPTEFTXFPTEFRXFTHFRXFFFRXFEFTXFTHFTXFFFTXFEF 
Access RRRRRRRR 
Reset 00000000 

Bit 9 – RXFTHF2 Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)

ValueDescription
0

Number of unread data in Receive FIFO is above RXFTHRES threshold.
1

Number of unread data in Receive FIFO has reached RXFTHRES2 threshold since the last RSTSTA command was issued.

Bit 8 – TXFLOCK Transmit FIFO Lock

ValueDescription
0

The Transmit FIFO is not locked.
1

The Transmit FIFO is locked.

Bit 7 – RXFPTEF Receive FIFO Underflow Error Flag

See FIFO Overflow/Underflow Error for details.

ValueDescription
0

No Receive FIFO underflow occurred.
1

Receive FIFO underflow error occurred due to an incorrect software access (read data exceeding available data in FIFO). Receiver must be reset by writing FLEX_SPI_CR.SWRST=1.

Bit 6 – TXFPTEF Transmit FIFO Overflow Error Flag

See FIFO Overflow/Underflow Error for details.

ValueDescription
0

No Transmit FIFO overflow occurred.
1

Transmit FIFO overflow error occurred due to an incorrect software access (written data exceeding available space). Transceiver must be reset by writing FLEX_SPI_CR.SWRST=1.

Bit 5 – RXFTHF Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)

ValueDescription
0

Number of unread data in Receive FIFO is below RXFTHRES threshold.
1

Number of unread data in Receive FIFO has reached RXFTHRES threshold since the last RSTSTA command was issued.

Bit 4 – RXFFF Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)

ValueDescription
0

Receive FIFO is not empty.
1

Receive FIFO has been filled since the last RSTSTA command was issued.

Bit 3 – RXFEF Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)

ValueDescription
0

Receive FIFO is not empty.
1

Receive FIFO has been emptied since the last RSTSTA command was issued.

Bit 2 – TXFTHF Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)

ValueDescription
0

Number of data in Transmit FIFO is above TXFTHRES threshold.
1

Number of data in Transmit FIFO has reached TXFTHRES threshold since the last RSTSTA command was issued.

Bit 1 – TXFFF Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)

ValueDescription
0

Transmit FIFO is not full.
1

Transmit FIFO has been filled since the last RSTSTA command was issued.

Bit 0 – TXFEF Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)

ValueDescription
0

Transmit FIFO is not empty.
1

Transmit FIFO has been emptied since the last RSTSTA command was issued.