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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
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2
CPU and Interconnect
2.3
Bus Matrix (MATRIX)
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
2.1
Arm926EJ-S Processor
2.2
Debug and Test
2.3
Bus Matrix (MATRIX)
2.3.1
Description
2.3.2
Embedded Characteristics
2.3.3
Special Bus Granting Techniques
2.3.4
No Default Host
2.3.5
Last Access Host
2.3.6
Fixed Default Host
2.3.7
Arbitration
2.3.8
Register Write Protection
2.3.9
Register Summary
2.4
DMA Controller (XDMAC)
2.5
Boot Strategies
3
Memories
4
System Controller
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
2.3 Bus Matrix (MATRIX)
