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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
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7
Security and Cryptography Subsystem
7.3
Secure Hash Algorithm (SHA)
7.3.4
Functional Description
7.3.4.10
Security Features
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
7.1
Overview
7.2
Advanced Encryption Standard (AES)
7.3
Secure Hash Algorithm (SHA)
7.3.1
Description
7.3.2
Embedded Characteristics
7.3.3
Product Dependencies
7.3.4
Functional Description
7.3.4.1
SHA Algorithm
7.3.4.2
HMAC Algorithm
7.3.4.3
Processing Period
7.3.4.4
Double Input Buffer
7.3.4.5
Internal Registers for Initial Hash Value or Expected Hash Result
7.3.4.6
Automatic Padding
7.3.4.7
Automatic Check
7.3.4.8
Protocol Layers Improved Performances
7.3.4.9
Start Modes
7.3.4.10
Security Features
7.3.4.10.1
Unspecified Register Access Detection
7.3.4.10.2
Register Write Protection
7.3.4.10.3
Security and Safety Analysis and Reports
7.3.5
Register Summary
7.4
Triple Data Encryption Standard (TDES)
7.5
Random Number Generator (TRNG)
7.6
Physical Unclonable Functions (PUF)
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
7.3.4.10 Security Features
