2.8.1 Common Functionality

The basic operation of USART is similar for both families, but the register and bit names are different. The AVR Dx devices have an improved register structure that allows a more efficient access to the configuration/status bits.

The following section details the mapping of ATmega128 registers into AVR Dx register structure (only ATmega registers and AVR Dx correspondences are figured):

megaAVR®AVR® DxDescription
RXBn (UDRn read)USARTn.RXDATALReceiver Data Register Low Byte
TXBn (UDRn write)USARTn.TXDATALTransmit Data Register Low Byte
UCSRnB.RXB8nUSARTn.RXDATAH.DATA[8]Receive Data Bit 8
UCSRnB.TXB8nUSARTn.TXDATAH.DATA[8]Transmit Data Bit 8
UCSRnB.UCSZn[2]USARTn.CTRLC.CHSIZE[2:0](1)USART Character Size
UCSRnC.UCSZn[1:0]
UCSRnB.RXENnUSARTn.CTRLC.RXENReceiver Enable
UCSRnB.TXENnUSARTn.CTRLC.TXENTransmitter Enable
UCSRnB.RXCIENnUSARTn.CTRLA.RXCIERX Complete Interrupt Enable
UCSRnB.TXCIENnUSARTn.CTRLA.TXCIETX Complete Interrupt Enable
UCSRnB.UDRIENnUSARTn.CTRLA.DREIEUSART Data Register Empty Interrupt Enable
UCSRnA.RXCnUSART.STATUS.RXCIFUSART Receive Complete Flag
UCSRnA.TXCnUSART.STATUS.TXCIFUSART Transmit Complete Flag
UCSRnA.UDREnUSART.STATUS.DREIFUSART Data Register Empty Flag
UCSRnA.FEnUSARTn.RXDATAH.FERRFraming Error
UCSRnA.DORnUSARTn.RXDATAH.BUFOVFData OverRun
UCSRnA.UPEnUSARTn.RXDATAH.PERRParity Error
UCSRnA.U2XnUSARTn.CTRLB.RXMODE[1:0] = CLK2XDouble the USART operation Speed
UCSRnA.MPCMnUSARTn.CTRLB.MPCMMulti-Processor Communication mode
UCSRnC.UMSELnUSARTn.CTRLC.CMODE[1:0](2)USART Mode Select
UCSRnC.UPMn[1:0]USARTn.CTRLC.PMODE[1:0]Parity Mode
UCSRnC.UBSnUSARTn.CTRLC.SBMODEStop Bit Mode
UCSRnC.UCPOLnUSARTn.CTRLC.UCPHA(3)Clock Polarity (SYNC MODE)
UBRRn[11:0]USARTn.BAUD[15:0](4)Baud Rate registers
Note:
  1. The settings are different for 9-bit operations.
  2. ASYNCH and SYNCH modes only.
  3. Only in Synchronous mode.
  4. The baud rate formula is different. Refer to the device data sheet for details.

The following code snippets shows the initialization of the USART peripheral for both families:

megaAVR® - USART Initialization (9600N1)

#define USART_BAUDRATE 9600   
#define BAUD_PRESCALE (((F_CPU / (USART_BAUDRATE * 16UL))) - 1)

void USART_Init(void){
   /* Set baud rate */
   UBRRL = BAUD_PRESCALE;             /* Load lower 8 bits into the low byte of the UBRR register */
   UBRRH = (BAUD_PRESCALE >> 8);      /* Load upper 8 bits into the high byte of the UBRR register */

   UCSRB = (1<<RXEN)|(1<<TXEN);       /* Enable receiver and transmitter */
   UCSRC = (1<<USBS)|(3<<UCSZ0);      /* Set frame format: 8data, 1 stop bit */
}

AVR® Dx - USART Initialization (9600N1)

#define USART1_BAUD_RATE(BAUD_RATE)     ((float)(64 * 4000000 / (16 * (float)BAUD_RATE)) + 0.5)

void USART1_init(void)
{
    USART1.BAUD = (uint16_t)(USART1_BAUD_RATE(9600));   /* set the baud rate*/
    
    USART1.CTRLC = USART_CHSIZE0_bm
                 | USART_CHSIZE1_bm; /* set the data format to 8-bit*/
                 
    USART1.CTRLB |= USART_RXEN_bm | USART_TXEN_bm;      /* enable receiver and transmitter*/
}