15.11.3 Generator Control
| Name: | GENCTRLn |
| Offset: | 0x20 + n*0x04 [n=0..4] |
| Reset: | 0x00010005 for Generator n=0, else 0x00000000 |
| Property: | PAC Write-Protection, Write-Synchronized |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DIV[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DIV[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RUNSTDBY | DIVSEL | OE | OOV | IDC | GENEN | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | x |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SRC[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | x | x | x | x | |||||
Bits 31:16 – DIV[15:0] Division Factor
These bits represent a division value for the corresponding Generator. The actual division factor is dependent on the state of DIVSEL. The number of relevant DIV bits for each Generator can be seen in this table. Written bits outside of the specified range will be ignored.
| Generic Clock Generator | Division Factor Bits |
|---|---|
| Generator 0 | 8 division factor bits - DIV[7:0] |
| Generator 1 | 16 division factor bits - DIV[15:0] |
| Generator 2 - 4 | 8 division factor bits - DIV[7:0] |
Bit 13 – RUNSTDBY Run in Standby
This bit is used to keep the Generator running in Standby as long as it is configured to output to a dedicated GCLK_IO pin. If GENCTRLn.OE is zero, this bit has no effect and the generator will only be running if a peripheral requires the clock.
| Value | Description |
|---|---|
| 0 | The Generator is stopped in Standby and the GCLK_IO pin state (one or zero) will be dependent on the setting in GENCTRL.OOV. |
| 1 | The Generator is kept running and output to its dedicated GCLK_IO pin during Standby mode. |
Bit 12 – DIVSEL Divide Selection
This bit determines how the division factor of the clock source of the Generator will be calculated from DIV. If the clock source should not be divided, DIVSEL must be 0 and the GENCTRLn.DIV value must be either 0 or 1.
| Value | Description |
|---|---|
| 0 | The Generator clock frequency equals the clock source frequency divided by GENCTRLn.DIV. |
| 1 | The Generator clock frequency equals the clock source frequency divided by 2^(GENCTRLn.DIV+1). |
Bit 11 – OE Output Enable
This bit is used to output the Generator clock output to the corresponding pin (GCLK_IO), as long as GCLK_IO is not defined as the Generator source in the GENCTRLn.SRC bit field.
| Value | Description |
|---|---|
| 0 | No Generator clock signal on pin GCLK_IO. |
| 1 | The Generator clock signal is output on the corresponding GCLK_IO, unless GCLK_IO is selected as a generator source in the GENCTRLn.SRC bit field. |
Bit 10 – OOV Output Off Value
This bit is used to control the clock output value on pin (GCLK_IO) when the Generator is turned off or the OE bit is zero, as long as GCLK_IO is not defined as the Generator source in the GENCTRLn.SRC bit field.
| Value | Description |
|---|---|
| 0 | The GCLK_IO will be LOW when generator is turned off or when the OE bit is zero. |
| 1 | The GCLK_IO will be HIGH when generator is turned off or when the OE bit is zero. |
Bit 9 – IDC Improve Duty Cycle
This bit is used to improve the duty cycle of the Generator output to 50/50 for odd division factors.
| Value | Description |
|---|---|
| 0 | Generator output clock duty cycle is not balanced to 50/50 for odd division factors. |
| 1 | Generator output clock duty cycle is 50/50. |
Bit 8 – GENEN Generator Enable
This bit is used to enable and disable the Generator.
| Value | Description |
|---|---|
| 0 | Generator is disabled. |
| 1 | Generator is enabled. |
Bits 3:0 – SRC[3:0] Generator Clock Source Selection
These bits select the Generator clock source, as shown in this table.
| Value | Name | Description |
|---|---|---|
| 0x0 | XOSC | XOSC oscillator output |
| 0x1 | GCLK_IN | Generator input pad (GCLK_IO) |
| 0x2 | GCLK_GEN1 | Generic clock generator 1 output |
| 0x3 | OSCULP32K | OSCULP32K oscillator output |
| 0x4 | XOSC32K | XOSC32K oscillator output |
| 0x5 | OSC16M | OSC16M oscillator output |
| 0x6 | DFLL48M | DFLL48M output |
| 0x7 | DPLL96M | DPLL96M output |
| 0x8-0xF | Reserved | Reserved for future use |
A Power Reset will reset all GENCTRLn registers. the Reset values of the GENCTRLn registers are shown in table below.
| GCLK Generator | Reset Value after a Power Reset |
|---|---|
| 0 | 0x00010005 |
| others | 0x00000000 |
A User Reset will reset the associated GENCTRL register unless the Generator is the source of a locked Peripheral Channel (PCHCTRLm.WRTLOCK=1). The reset values of the GENCTRL register are as shown in the table below.
| GCLK Generator | Reset Value after a User Reset |
|---|---|
| 0 | 0x00000105 |
| others | No change
if the generator is used by a Peripheral Channel m with
PCHCTRLm.WRTLOCK=1 else 0x00000000 |