15.11.4 Peripheral Channel Control

PCHTRLm controls the settings of Peripheral Channel number m (m = 0..28).

Name:	PCHCTRLm
Offset:	0x80 + m*0x04 [m=0..28]
Reset:	0x00000000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	WRTLOCK	CHEN			GEN[3:0]
Access	R/W	R/W			R/W	R/W	R/W	R/W
Reset	0	0			0	0	0	0

Bit 7 – WRTLOCK Write Lock

After this bit is set to '1', further writes to the PCHCTRLm register will be discarded. The control register of the corresponding Generator n (GENCTRLn), as assigned in PCHCTRLm.GEN, will also be locked. It can only be unlocked by a Power Reset.

Note that Generator 0 cannot be locked.

Value	Description
0	The Peripheral Channel register and the associated Generator register are not locked
1	The Peripheral Channel register and the associated Generator register are locked

Bit 6 – CHEN Channel Enable

This bit is used to enable and disable a Peripheral Channel.

Value	Description
0	The Peripheral Channel is disabled
1	The Peripheral Channel is enabled

Bits 3:0 – GEN[3:0] Generator Selection

This bit field selects the Generator to be used as the source of a peripheral clock, as shown in the table below:

Table 15-7. Generator Selection
Value	Description
0x0	Generic Clock Generator 0
0x1	Generic Clock Generator 1
0x2	Generic Clock Generator 2
0x3	Generic Clock Generator 3
0x4	Generic Clock Generator 4
0x5 - 0xF	Reserved

Table 15-8. Reset Value after a User Reset or a Power Reset
Reset	PCHCTRLm.GEN	PCHCTRLm.CHEN	PCHCTRLm.WRTLOCK
Power Reset	0x0	0x0	0x0
User Reset	If WRTLOCK = 0 : 0x0 If WRTLOCK = 1: no change	If WRTLOCK = 0 : 0x0 If WRTLOCK = 1: no change	No change

A Power Reset will reset all the PCHCTRLm registers.

A User Reset will reset a PCHCTRL if WRTLOCK = 0, or else, the content of that PCHCTRL remains unchanged.

The PCHCTRL register Reset values are shown in the table PCHCTRLm Mapping.

Table 15-9. PCHCTRLm Mapping
index(m)	Name	Description
0	GCLK_DFLL48M_REF	DFLL48M Reference
1	GCLK_FDPLL	FDPLL96M input clock source for reference
2	GCLK_FDPLL_32K	FDPLL96M 32kHz clock for FDPLL96M internal lock timer
3	GCLK_EIC	EIC
4	GCLK_FREQM_MSR	FREQM Measure
5	GCLK_FREQM_REF	FREQM Reference
6	GLCK_USB	USB
7	GCLK_EVSYS_CHANNEL_0	EVSYS_CHANNEL_0
8	GCLK_EVSYS_CHANNEL_1	EVSYS_CHANNEL_1
9	GCLK_EVSYS_CHANNEL_2	EVSYS_CHANNEL_2
10	GCLK_EVSYS_CHANNEL_3	EVSYS_CHANNEL_3
11	GCLK_EVSYS_CHANNEL_4	EVSYS_CHANNEL_4
12	GCLK_EVSYS_CHANNEL_5	EVSYS_CHANNEL_5
13	GCLK_EVSYS_CHANNEL_6	EVSYS_CHANNEL_6
14	GCLK_EVSYS_CHANNEL_7	EVSYS_CHANNEL_7
15	GCLK_SERCOM[0,1,2,3,4,5]_SLOW	SERCOM[0,1,2,3,4,5]_SLOW
16	GCLK_SERCOM0_CORE	SERCOM0_CORE
17	GCLK_SERCOM1_CORE	SERCOM1_CORE
18	GCLK_SERCOM2_CORE	SERCOM2_CORE
19	GCLK_SERCOM3_CORE	SERCOM3_CORE
20	GCLK_SERCOM4_CORE	SERCOM4_CORE
21	GCLK_SERCOM5_CORE	SERCOM5_CORE
22	GCLK_TCC0	TCC0
23	GCLK_TC0, GCLK_TC1	TC0, TC1
24	GCLK_TC2, GCLK_TC3	TC2, TC3
25	GCLK_ADC	ADC
26	GCLK_AC	AC
27	GCLK_PTC	PTC
28	GCLK_CCL	CCL