19.8.7 Standby Configuration
| Name: | STDBYCFG |
| Offset: | 0x08 |
| Reset: | 0x0400 |
| Property: | PAC Write-Protection |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BBIASHS[1:0] | |||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| VREGSMOD[1:0] | |||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 | |||||||
Bits 11:10 – BBIASHS[1:0] Back Bias for HMCRAMCHS
Refer to Table 19-4 for details.
| Value | Description |
|---|---|
| 0 | No Back Biasing in Standby mode |
| 1 | Back Biasing in Standby mode |
| 2 | Standby OFF mode |
| 3 | Always OFF mode |
Bits 7:6 – VREGSMOD[1:0] VREG Switching Mode
Refer to Regulator Automatic Low-Power Mode for details.
| Value | Name | Description |
|---|---|---|
| 0x0 | AUTO | Automatic Mode |
| 0x1 | PERFORMANCE | Performance oriented |
| 0x2 | LP | Low Power consumption oriented |