19.8.3 Performance Level Configuration
| Name: | PLCFG |
| Offset: | 0x02 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PLDIS | PLSEL[1:0] | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bit 7 – PLDIS Performance Level Disable
Disabling the PL selection forces the device to run in PL0, reducing the power consumption, and the wake-up time from Standby Sleep mode.
Changing this bit when the current performance level is not PL0 is discarded, and a violation is reported to the PAC module.
| Value | Description |
|---|---|
| 0 | The Performance Level mechanism is enabled. |
| 1 | The Performance Level mechanism is disabled. |
Bits 1:0 – PLSEL[1:0] Performance Level Select
| Value | Name | Definition |
|---|---|---|
| 0x0 | PL0 | Performance Level 0 |
| 0x1 | Reserved | Reserved |
| 0x2 | PL2 | Performance Level 2 |
| 0x3 | Reserved | Reserved |