42.5.3 Clocks

The SLCD bus clock (CLK_SLCD_APB) can be enabled and disabled in the Main Clock module MCLK, and the default state of CLK_SLCD_APB can be found in Peripheral Clock Masking section.

A 32.768kHz oscillator clock (CLK_SLCD_OSC) is required to clock the SLCD. This clock must be configured and enabled in the 32KHz oscillator controller (OSC32KCTRL) before using the SLCD.

This oscillator clock is asynchronous to the bus clock (CLK_SLCD_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains.