25.8.19 Channel Control B

This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Name: CHCTRLB
Offset: 0x44
Reset: 0x00000000
Property: PAC Write Protection, Enable-Protected

Bit 3130292827262524 
       CMD[1:0] 
Access R/WR/W 
Reset 00 
Bit 2322212019181716 
 TRIGACT[1:0]       
Access R/WR/W 
Reset 00 
Bit 15141312111098 
   TRIGSRC[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 76543210 
  LVL[1:0]EVOEEVIEEVACT[2:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bits 23:22 – TRIGACT[1:0] Trigger Action

These bits define the trigger action used for a transfer.

TRIGACT[1:0]NameDescription
0x0BLOCKOne trigger required for each block transfer
0x1-Reserved
0x2BEATOne trigger required for each beat transfer
0x3TRANSACTIONOne trigger required for each transaction

Bits 13:8 – TRIGSRC[5:0] Trigger Source

These bits define the peripheral trigger which is source of the transfer. For details on trigger selection and trigger modes, refer to Transfer Triggers and Actions and CHCTRLB.TRIGACT.

ValueNameDescription
0x00DISABLEOnly software/event triggers
0x01RTC TIMESTAMPRTC Timestamp Trigger
0x02SERCOM0 RXSERCOM0 RX Trigger
0x03SERCOM0 TXSERCOM0 TX Trigger
0x04SERCOM1 RXSERCOM1 RX Trigger
0x05SERCOM1 TXSERCOM1 TX Trigger
0x06SERCOM2 RXSERCOM2 RX Trigger
0x07SERCOM2 TXSERCOM2 TX Trigger
0x08SERCOM3 RXSERCOM3 RX Trigger
0x09SERCOM3 TXSERCOM3 TX Trigger
0x0ASERCOM4 RXSERCOM4 RX Trigger
0x0BSERCOM4 TXSERCOM4 TX Trigger
0c0CSERCOM5 RXSERCOM5 RX Trigger
0x0DSERCOM5 TXSERCOM5 TX Trigger
0x0ETCC0 OVFTCC0 Overflow Trigger
0x0FTCC0 MC0TCC0 Match/Compare 0 Trigger
0x10TCC0 MC1TCC0 Match/Compare 1 Trigger
0x11TCC0 MC2TCC0 Match/Compare 2 Trigger
0x12TCC0 MC3TCC0 Match/Compare 3 Trigger
0x13TC0 OVFTC0 Overflow Trigger
0x14TC0 MC0TC0 Match/Compare 0 Trigger
0x15TC0 MC1TC0 Match/Compare 1 Trigger
0x16TC1 OVFTC1 Overflow Trigger
0x17TC1 MC0TC1 Match/Compare 0 Trigger
0x18TC1 MC1TC1 Match/Compare 1 Trigger
0x19TC2 OVFTC2 Overflow Trigger
0x1ATC2 MC0TC2 Match/Compare 0 Trigger
0x1BTC2 MC1TC2 Match/Compare 1 Trigger
0x1CTC3 OVFTC3 Overflow Trigger
0x1DTC3 MC0TC3 Match/Compare 0 Trigger
0x1ETC3 MC1TC3 Match/Compare 1 Trigger
0x1FADC RESRDYADC Result Ready Trigger
0x20SLCD DMUSLCD Display Memory Update Trigger
0x21SLCD ACMDRDYSLCD Automated Character Mapping Data Ready Trigger
0x22SLCD ABMDRDYSLCD Automated Bit Mapping Data Ready Trigger
0x23AES WRAES Write Trigger
0x24AES RDAES Read Trigger
0x25PTC EOCPTC End of Conversion Trigger
0x26PTC SEQPTC Sequence Trigger
0x27PTC WCOMPPTC Window Comparator Trigger

Bits 6:5 – LVL[1:0] Channel Arbitration Level

These bits define the arbitration level used for the DMA channel, where a high level has priority over a low level. For further details on arbitration schemes, refer to 25.6.2.4 Arbitration.

These bits are not enable-protected.

TRIGACT[1:0]NameDescription
0x0LVL0Channel Priority Level 0
0x1LVL1Channel Priority Level 1
0x2LVL2Channel Priority Level 2
0x3LVL3Channel Priority Level 3

Bit 4 – EVOE Channel Event Output Enable

This bit indicates if the Channel event generation is enabled. The event will be generated for every condition defined in the descriptor Event Output Selection (BTCTRL.EVOSEL).

This bit is available only for the Least Significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details.

ValueDescription
0Channel event generation is disabled
1Channel event generation is enabled

Bit 3 – EVIE Channel Event Input Enable

This bit is available only for the Least Significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details.

ValueDescription
0Channel event action will not be executed on any incoming event
1Channel event action will be executed on any incoming event

Bits 2:0 – EVACT[2:0] Event Input Action

These bits define the event input action, as shown below. The action is executed only if the corresponding EVIE bit in CHCTRLB register of the channel is set.

These bits are available only for the Least Significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details.

EVACT[2:0]NameDescription
0x0NOACTNo action
0x1TRIGNormal Transfer and Conditional Transfer on Strobe trigger
0x2CTRIGConditional transfer trigger
0x3CBLOCKConditional block transfer
0x4SUSPENDChannel suspend operation
0x5RESUMEChannel resume operation
0x6SSKIPSkip next block suspend action
0x7-Reserved