9.2 Physical Memory Map

The high-speed bus is implemented as a bus matrix. All high-speed bus addresses are fixed, and they are never remapped in any way, even during boot. The 32-bit physical address space is mapped as follows:

Table 9-1. SAM L22 Physical Memory Map
Memory	Start address	Size [KB]
Memory	Start address	SAML22x18⁽¹⁾	SAML22x17⁽¹⁾	SAML22x16⁽¹⁾
Embedded Flash	0x00000000	256	128	64
Embedded RWW section	0x00400000	8	4	2
Embedded SRAM	0x20000000	32	16	8
Peripheral Bridge A	0x40000000	64	64	64
Peripheral Bridge B	0x41000000	64	64	64
Peripheral Bridge C	0x42000000	64	64	64
IOBUS	0x60000000	0.5	0.5	0.5

Note: 1. x = G, J, or N.

Table 9-2. Flash Memory Parameters
Device	Flash size [KB]	Number of pages	Page size [Bytes]
SAML22x18⁽¹⁾	256	4096	64
SAML22x17⁽¹⁾	128	2048	64
SAML22x16⁽¹⁾	64	1024	64

Note: 1. x = G, J, or N.

Table 9-3. RWW Section Parameters⁽¹⁾
Device	Flash size [KB]	Number of pages	Page size [Bytes]
SAML22x18⁽¹⁾	8	128	64
SAML22x17⁽¹⁾	4	64	64
SAML22x16⁽¹⁾	2	32	64

Note: 1. x = G, J, or N.