28.8.10 Control
Tip: The I/O pins are assembled
in pin groups (”PORT groups”) with up to 32 pins. Group 0 consists of the PA pins, group
1 is for the PB pins, and so on. Each pin group has its own PORT registers, with a 0x80
address spacing. For example, the register address offset for the Data Direction (DIR)
register for group 0 (PA00 to PA31) is 0x00, and the register address offset for the DIR
register for group 1 (PB00 to PB31) is 0x80.
| Name: | CTRL |
| Offset: | 0x24 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SAMPLING[31:24] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SAMPLING[23:16] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SAMPLING[15:8] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SAMPLING[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:0 – SAMPLING[31:0] Input Sampling Mode
Configures the input sampling functionality of the I/O pin input samplers, for pins configured as inputs through the Data Direction register (DIR).
The input samplers are enabled and disabled in sub-groups of eight. Thus if any pins within a byte request continuous sampling, all pins in that eight pin sub-group will be continuously sampled.
| Value | Description |
|---|---|
| 0 | The I/O pin input synchronizer is disabled. |
| 1 | The I/O pin input synchronizer is enabled. |