32.8.1 Control A

Name: CTRLA
Offset: 0x00
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized

Bit 3130292827262524 
  DORDCPOLCPHAFORM[3:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 2322212019181716 
   DIPO[1:0]  DOPO[1:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 15141312111098 
        IBON 
Access R/W 
Reset 0 
Bit 76543210 
 RUNSTDBY  MODE[2:0]ENABLESWRST 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 30 – DORD Data Order

This bit selects the data order when a character is shifted out from the shift register.

This bit is not synchronized.

ValueDescription
0 MSB is transferred first.
1 LSB is transferred first.

Bit 29 – CPOL Clock Polarity

In combination with the Clock Phase bit (CPHA), this bit determines the SPI transfer mode.

This bit is not synchronized.

ValueDescription
0 SCK is low when idle. The leading edge of a clock cycle is a rising edge, while the trailing edge is a falling edge.
1 SCK is high when idle. The leading edge of a clock cycle is a falling edge, while the trailing edge is a rising edge.

Bit 28 – CPHA Clock Phase

In combination with the Clock Polarity bit (CPOL), this bit determines the SPI transfer mode.

This bit is not synchronized.

Mode CPOL CPHA Leading Edge Trailing Edge
0x0 0 0 Rising, sample Falling, change
0x1 0 1 Rising, change Falling, sample
0x2 1 0 Falling, sample Rising, change
0x3 1 1 Falling, change Rising, sample
ValueDescription
0 The data is sampled on a leading SCK edge and changed on a trailing SCK edge.
1 The data is sampled on a trailing SCK edge and changed on a leading SCK edge.

Bits 27:24 – FORM[3:0] Frame Format

This bit field selects the various frame formats supported by the SPI in Client mode. When the 'SPI frame with address' format is selected, the first byte received is checked against the ADDR register.

FORM[3:0] Name Description
0x0 SPI SPI frame
0x1 - Reserved
0x2 SPI_ADDR SPI frame with address
0x3-0xF - Reserved

Bits 21:20 – DIPO[1:0] Data In Pinout

These bits define the data in (DI) pad configurations.

In Host operation, DI is MISO.

In Client operation, DI is MOSI.

These bits are not synchronized.

DIPO[1:0] Name Description
0x0 PAD[0] SERCOM PAD[0] is used as data input
0x1 PAD[1] SERCOM PAD[1] is used as data input
0x2 PAD[2] SERCOM PAD[2] is used as data input
0x3 PAD[3] SERCOM PAD[3] is used as data input

Bits 17:16 – DOPO[1:0] Data Out Pinout

This bit defines the available pad configurations for data out (DO) and the serial clock (SCK). In Client operation, the Client select line (SS) is controlled by DOPO, while in Host operation the SS line is controlled by the port configuration.

In Host operation, DO is MOSI.

In Client operation, DO is MISO.

These bits are not synchronized.

DOPO DO SCK Client SS Host SS
0x0 PAD[0] PAD[1] PAD[2] System configuration
0x1 PAD[2] PAD[3] PAD[1] System configuration
0x2 PAD[3] PAD[1] PAD[2] System configuration
0x3 PAD[0] PAD[3] PAD[1] System configuration

Bit 8 – IBON Immediate Buffer Overflow Notification

This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is set when a buffer overflow occurs.

This bit is not synchronized.

ValueDescription
0 STATUS.BUFOVF is set when it occurs in the data stream.
1 STATUS.BUFOVF is set immediately upon buffer overflow.

Bit 7 – RUNSTDBY Run In Standby

This bit defines the functionality in standby sleep mode.

These bits are not synchronized.

RUNSTDBY Client Host
0x0 Disabled. All reception is dropped, including the ongoing transaction. Generic clock is disabled when ongoing transaction is finished. All interrupts can wake up the device.
0x1 Ongoing transaction continues, wake on Receive Complete interrupt. Generic clock is enabled while in sleep modes. All interrupts can wake up the device.

Bits 4:2 – MODE[2:0] Operating Mode

These bits must be written to 0x2 or 0x3 to select the SPI serial communication interface of the SERCOM.

0x2: SPI Client operation

0x3: SPI Host operation

These bits are not synchronized.

Bit 1 – ENABLE Enable

Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the Synchronization Enable Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE is cleared when the operation is complete.

This bit is not enable-protected.

ValueDescription
0 The peripheral is disabled or being disabled.
1 The peripheral is enabled or being enabled.

Bit 0 – SWRST Software Reset

Writing '0' to this bit has no effect.

Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled.

Writing ''1' to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register.

Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY. SWRST will both be cleared when the reset is complete.

This bit is not enable-protected.

ValueDescription
0 There is no reset operation ongoing.
1 The reset operation is ongoing.