2 I2C Mode Overview

The MSSP’s I2C module provides a synchronous serial interface between the microcontroller and other I2C-compatible devices using a two-wire bus network. The two signal connections, Serial Clock (SCL) and Serial Data (SDA), are bidirectional open-drain lines, each requiring pull-up resistors to the supply voltage. Pulling the signal line to ground is considered a logic ‘0’, while allowing the signal line to float is considered a logic ‘1’.

Figure 2-1 shows a typical connection between a master and a slave.

Figure 2-1. I2C Master/Slave Connection
Important: Due to the variety of device technologies (e.g., CMOS, NMOS), the logic voltage levels (logic low (0), logic high (1)) are not fixed, but rather are proportional to the bus supply voltage.

According to the I2C Specification, a logic input low level (VIL) is up to 30% of VDD (VIL ≤ 0.3VDD), while a logic input high level (VIH) is between 70% and 100% of VDD (VIH ≥ 0.7VDD). Some legacy devices may use the previously defined fixed levels of VIL = 1.5V and VIH = 3.0V. However, all new I2C-compatible devices must adhere to the 30/70% specification.

All I2C communication is performed using an 8-bit data word and a 1-bit Acknowledge condition. All transactions are initiated and terminated by the master device. Address and data are transmitted starting with the Most Significant bit (MSb). Depending on the direction of the data being transferred, there are four main operations performed in I2C mode:
  • Master Transmit - master is sending data to a slave
  • Master Receive - master is receiving data from a slave
  • Slave Transmit - slave is sending data to a master
  • Slave Receive - slave is receiving data from a master
The I2C Specification also defines three message protocols:
  • Single message where a master writes data to a slave
  • Single message where a master reads data from a slave
  • Combined message where a master initiates a minimum of two writes, two reads, or a combination of reads and writes, to one or more slaves.

Communication begins when a master device transmits a Start condition, followed by the address of the slave it intends to communicate with. Bit 0 in the 7-bit address byte, or Bit 0 of the high address byte in 10-bit Addressing mode, is reserved as the Read/Write Information (R/W) bit. The R/W bit determines whether the master intends to write data to a slave (R/W = 0) or receive data from the slave (R/W = 1).

If the requested slave device exists on the bus, it will respond with an Acknowledge sequence (ACK). The ACK sequence takes place during the 9th clock pulse and indicates to the transmitting device that the receiving device is active and ready for communication.

In Master Transmit mode, the master will continue to send data to the slave, and the receiver will continue to respond with an ACK, as long as the data is considered valid. In Master Receive mode, the master will continue to receive data from the slave and will respond to the slave with an ACK. When the master transmits or receives the last byte of data, it can end communication by issuing a Stop condition, or it can issue a Restart condition if it intends to continue to communicate with the bus.

The I2C Specification allows for a multi-master bus, meaning that there can be several master devices connected to a single bus. A master can select a slave device by transmitting a unique address on the bus. When the address matches a slave’s address, the slave responds with an ACK and communication between the master and slave can commence. All other devices on the bus must ignore any transactions not intended for them.