1.1 I2C Terminology
To properly understand the language used in the Specification, Table 1-1 shows a list of commonly used terms found throughout the Specification.
| Term | Description |
|---|---|
| Transmitter | The device that shifts data out onto the bus. |
| Receiver | The device that shifts data in from the bus. |
| Master | The device that generates the clock signal (SCL), initiates data transfer and terminates transmission. |
| Slave | The device addressed by the master. |
| Multi-Master | A bus that contains at least two master devices, both of which can initiate communications. |
| Arbitration | A procedure that ensures that only one master device at a time can control the bus. |
| Synchronization | A procedure that synchronizes the clock signals of two or more devices on the bus. |
| Idle | Both SDA and SCL signals are at a logic high state and there is no activity on the bus. |
| Active | The state of the bus during which communication takes place. |
| Write Request | A master device transmits a slave address with the R/W bit clear with the intention of transmitting data to a slave. |
| Read Request | A master device transmits a slave address with the R/W bit set with the intention of receiving data from a slave. |
| Clock Stretching | Occurs when a device pulls the SCL line low to effectively pause communications. |
| Bus Collision | The condition in which the expected SDA logic level is high, but is actually sampled as a logic low. |
| Bus Timeout | The condition in which a device is holding the bus for longer than a specified period. |