3 Signal Description
| Signal Name | Function | Type | Comments | Active Level |
|---|---|---|---|---|
| Clocks, Oscillators and PLLs | ||||
| XIN | Main Oscillator Input | Input | – | – |
| XOUT | Main Oscillator Output | Output | – | – |
| XIN32 | Slow Clock Oscillator Input | Input | – | – |
| XOUT32 | Slow Clock Oscillator Output | Output | – | – |
| CLK_AUDIO | Audio Clock | Output | – | – |
| VBG | Bias Voltage Reference for USB | Analog | – | – |
| PCK 0–2 | Programmable Clock Output | Output |
Reset state: - PIO Input - Internal Pull-up enabled - Schmitt Trigger enabled | – |
| Shutdown, Wake-up Logic | ||||
| SHDN | Shutdown Control | Output | – | – |
| PIOBU 0–7 | Tamper or Wake-up Inputs | Input | – | – |
| WKUP | Wake-up Input | Input | – | – |
| ICE and JTAG | ||||
| TCK/SWCLK | Test Clock/Serial Wire Clock | Input | – | – |
| TDI | Test Data In | Input | – | – |
| TDO | Test Data Out | Output | – | – |
| TMS/SWDIO | Test Mode Select/Serial Wire Input/Output | I/O | – | – |
| JTAGSEL | JTAG Selection | Input | – | – |
| Reset/Test | ||||
| NRST | Microprocessor Reset | Input | – | Low |
| TST | Test Mode Select | Input | – | – |
| NTRST | Test Reset Signal | Input | – | – |
| Advanced Interrupt Controller - AIC | ||||
| IRQ | External Interrupt Input | Input | – | – |
| Secured Advanced Interrupt Controller - SAIC | ||||
| FIQ | Fast Interrupt Input | Input | – | – |
| PIO Controller - PIO | ||||
| PA0–PA31 | Parallel IO Controller | I/O | – | – |
| PB0–PB31 | Parallel IO Controller | I/O | – | – |
| PC0–PC31 | Parallel IO Controller | I/O | – | – |
| PD0–PD31 | Parallel IO Controller | I/O | – | – |
| External Bus Interface - EBI | ||||
| D[15:0] | Data Bus | I/O | – | – |
| A[25:0] | Address Bus | Output | – | – |
| NWAIT | External Wait Signal | Input | – | Low |
| Static Memory Controller - SMC | ||||
| NCS0–NCS3 | Chip Select Lines | Output | – | Low |
| NWR0–NWR1 | Write Signal | Output | – | Low |
| NRD | Read Signal | Output | – | Low |
| NWE | Write Enable | Output | – | Low |
| NBS0–NBS1 | Byte Mask Signal | Output | – | Low |
| NANDOE | NAND Flash Output Enable | Output | – | Low |
| NANDWE | NAND Flash Write Enable | Output | – | Low |
| DDR2/DDR3/LPDDR1/LPDDR2/LPDDR3 Controller | ||||
| DDR_CK, DDR_CLKN | DDR Differential Clock | Output | – | – |
| DDR_CKE | DDR Clock Enable | Output | When Backup Self-refresh (BSR) mode is used, should be tied to GND using 100 KΩ pull-down | High |
| DDR_CS | DDR Controller Chip Select | Output | – | Low |
| DDR_BA[2:0] | Bank Select | Output | – | Low |
| DDR_WE | DDR Write Enable | Output | – | Low |
| DDR_RAS, DDR_CAS | Row and Column Signal | Output | – | Low |
| DDR_A[13:0] | DDR Address Bus | Output | – | – |
| DDR_D[31:0] | DDR Data Bus | I/O/-PD | – | – |
| DDR_DQS[3:0], DDR_DQSN[3:0] | Differential Data Strobe | I/O- PD | – | – |
| DDR_DQM[3:0] | Write Data Mask | Output | – | – |
| DDR_CAL | DDR/LPDDR Calibration | Input | – | – |
| DDR_VREF | DDR/LPDDR Reference | Input | – | – |
| DDR_RESETN | DDR3 Active Low Asynchronous Reset | Output | When Backup Self-refresh (BSR) mode is used, should be tied to VDDIODDR using 100 KΩ pull-up | – |
| Secure Data Memory Card - SDMMCx [1:0] | ||||
| SDMMCx_CD | SDcard / e.MMC Card Detect | Input | – | – |
| SDMMCx_CMD | SDcard / e.MMC Command line | I/O | – | – |
| SDMMCx_WP | SDcard Connector Write Protect Signal | Input | – | – |
| SDMMCx_RSTN | e.MMC Reset Signal | Output | – | – |
| SDMMCx_1V8SEL | SDcard Signal Voltage Selection | Output | – | – |
| SDMMCx_CK | SDcard / e.MMC Clock Signal | Output | – | – |
| SDMMCx_DAT[7:0] | SDcard / e.MMC Data Lines | I/O | – | – |
| Flexible Serial Communication Controller - FLEXCOMx [4:0] | ||||
| FLEXCOMx_IO0 | FLEXCOMx Transmit Data | I/O | – | – |
| FLEXCOMx_IO1 | FLEXCOMx Receive Data | I/O | – | – |
| FLEXCOMx_IO2 | FLEXCOMx Serial Clock | I/O | – | – |
| FLEXCOMx_IO3 | FLEXCOMx Clear To Send / Peripheral Chip Select | I/O | – | – |
| FLEXCOMx_IO4 | FLEXCOMx Request To Send / Peripheral Chip Select | Output | – | – |
| Universal Asynchronous Receiver Transmitter - UARTx [4..0] | ||||
| UTXDx | UARTx Transmit Data | Output | – | – |
| URXDx | UARTx Receive Data | Input | – | – |
| Inter-IC Sound Controller - I2SCx [1..0] | ||||
| I2SCx_MCK | Main System Bus Clock | Output | – | – |
| I2SCx_CK | Serial Clock | I/O | – | – |
| I2SCx_WS | I2S Word Select | I/O | – | – |
| I2SCx_DI0 | Serial Data Input | Input | – | – |
| I2SCx_DO0 | Serial Data Output | Output | – | – |
| Synchronous Serial Controller - SSCx [1..0] | ||||
| TDx | SSC Transmit Data | Output | – | – |
| RDx | SSC Receive Data | Input | – | – |
| TKx | SSC Transmit Clock | I/O | – | – |
| RKx | SSC Receive Clock | I/O | – | – |
| TFx | SSC Transmit Frame Sync | I/O | – | – |
| RFx | SSC Receive Frame Sync | I/O | – | – |
| Timer/Counter - TCx [1..0] | ||||
| TCLK[5..0] | TC Channel y External Clock Input | Input | TCLK0 to TCLK2 for TC0 | – |
| TCLK3 to TCLK5 for TC1 | ||||
| TIOA[5..0] | TC Channel y I/O Line A | I/O | TIOA0 to TIOA2 for TC0 | – |
| TIOA3 to TIOA5 for TC1 | ||||
| TIOB[5..0] | TC Channel y I/O Line B | I/O | TIOB0 to TIOB2 for TC0 | – |
| TIOB3 to TIOB5 for TC1 | ||||
| Quad IO SPI - QSPIx [1..0] | ||||
| QSPIx_SCK | QSPI Serial Clock | Output | – | – |
| QSPIx_CS | QSPI Chip Select | Output | – | – |
| QSPIx_IO[0..3] | QSPI I/O QIO0 is QMOSI Host Out/Client In QIO1 is QMISO Host In/Client Out | I/O | – | – |
| Serial Peripheral Interface - SPIx [1..0] | ||||
| SPIx_MISO | Host In/Client Out | I/O | – | – |
| SPIx_MOSI | Host Out/Client In | I/O | – | – |
| SPIx_SPCK | SPI Serial Clock | I/O | – | – |
| SPIx_NPCS0 | SPI Peripheral Chip Select 0 | I/O | – | Low |
| SPIx_NPCS[3..1] | SPI Peripheral Chip Select | Output | – | Low |
| Two-wire Interface - TWIx [1..0] | ||||
| TWDx | Two-wire Serial Data | I/O | – | – |
| TWCKx | Two-wire Serial Clock | I/O | – | – |
| Pulse Width Modulation Controller - PWM | ||||
| PWMH0–3 | PWM Waveform Output High | Output | – | – |
| PWML0–3 | PWM Waveform Output Low | Output | – | – |
| PWMFI0–1 | PWM Fault Inputs | Input | – | – |
| PWMEXTRG1–2 | PWM External Trigger | Input | – | – |
| USB Host High-Speed Port - UHPHS | ||||
| HHSDPA | USB Host Port A High-Speed Data + | Analog | – | – |
| HHSDMA | USB Host Port A High-Speed Data - | Analog | – | – |
| HHSDPB | USB Host Port B High-Speed Data + | Analog | – | – |
| HHSDMB | USB Host Port B High-Speed Data - | Analog | – | – |
| USB Device High-Speed Port - UDPHS | ||||
| DHSDP | USB Device High-Speed Data + | Analog | – | – |
| DHSDM | USB Device High-Speed Data - | Analog | – | – |
| USB High-Speed Inter-Chip Port - HSIC | ||||
| HHSTROBE | USB High-Speed Inter-Chip Strobe | I/O | – | – |
| HHDATA | USB High-Speed Inter-Chip Data | I/O | – | – |
| Ethernet 10/100 - GMAC | ||||
| GREFCK | Reference Clock | Input | – | – |
| GTXCK | Transmit Clock | Input | – | – |
| GRXCK | Receive Clock | Input | – | – |
| GTXEN | Transmit Enable | Output | – | – |
| GTX0–GTX3 | Transmit Data | Output | – | – |
| GTXER | Transmit Coding Error | Output | – | – |
| GRXDV | Receive Data Valid | Input | – | – |
| GRX0–GRX3 | Receive Data | Input | – | – |
| GRXER | Receive Error | Input | – | – |
| GCRS | Carrier Sense | Input | – | – |
| GCOL | Collision Detected | Input | – | – |
| GMDC | Management Data Clock | Output | – | – |
| GMDIO | Management Data Input/Output | I/O | – | – |
| GTSUCOMP | TSU timer comparison valid | Output | – | – |
| LCD Controller - LCDC | ||||
| LCDDAT[23:0] | LCD Data Bus | Output | – | – |
| LCDVSYNC | LCD Vertical Synchronization | Output | – | – |
| LCDHSYNC | LCD Horizontal Synchronization | Output | – | – |
| LCDPCK | LCD Pixel Clock | Output | – | – |
| LCDDEN | LCD Data Enable | Output | – | – |
| LCDPWM | LCDPWM for Contrast Control | Output | – | – |
| LCDDISP | LCD Display ON/OFF | Output | – | – |
| Analog-to-Digital Controller - ADC | ||||
| AD0–11 | 12 Analog Inputs | Analog | – | – |
| ADTRG | ADC Trigger | Input | – | – |
| ADVREF | ADC Reference | Analog | – | – |
| Security Module - SECUMOD | ||||
| PIOBU0–7 | Tamper I/Os | I/O | – | – |
| Image Sensor Controller - ISC | ||||
| ISC_D0–ISC_D11 | Image Sensor Data | Input | – | – |
| ISC_HSYNC | Image Sensor Horizontal Synchro | Input | – | – |
| ISC_VSYNC | Image Sensor Vertical Synchro | Input | – | – |
| ISC_PCK | Image Sensor Pixel clock | Input | – | – |
| ISC_MCK | Image Sensor Main clock | Output | – | – |
| ISC_FIELD | Field identification signal | Input | – | – |
| Audio Class Amplifier - CLASSD | ||||
| CLASSD_L0 | CLASSD Left Output L0 | Output | – | – |
| CLASSD_L1 | CLASSD Left Output L1 | Output | – | – |
| CLASSD_L2 | CLASSD Left Output L2 | Output | – | – |
| CLASSD_L3 | CLASSD Left Output L3 | Output | – | – |
| CLASSD_R0 | CLASSD Right Output R0 | Output | – | – |
| CLASSD_R1 | CLASSD Right Output R1 | Output | – | – |
| CLASSD_R2 | CLASSD Right Output R2 | Output | – | – |
| CLASSD_R3 | CLASSD Right Output R3 | Output | – | – |
| Controller Area Network - CAN | ||||
| CANRXx | CAN Receive | Input | – | – |
| CANTXx | CAN Transmit | Output | – | – |
| Peripheral Touch Controller - PTC | ||||
| PTC_X[7..0] | X-lines | Output | – | – |
| PTC_Y[7..0] | Y-lines | Input | – | – |
| Pulse Density Modulation Interface Controller - PDMIC | ||||
| PDMIC_DAT | PDM Data | Input | – | – |
| PDMIC_CLK | PDM Clock | Output | – | – |