3 Signal Description

Table 3-1. Signal Description List
Signal NameFunctionTypeCommentsActive Level
Clocks, Oscillators and PLLs
XINMain Oscillator InputInput
XOUTMain Oscillator OutputOutput
XIN32Slow Clock Oscillator InputInput
XOUT32Slow Clock Oscillator OutputOutput
CLK_AUDIOAudio ClockOutput
VBGBias Voltage Reference for USBAnalog
PCK 0–2Programmable Clock OutputOutputReset State:

- PIO Input

- Internal Pull-up enabled

- Schmitt Trigger enabled

Shutdown, Wake-up Logic
SHDNShutdown ControlOutput
PIOBU 0–7Tamper or Wake-up InputsInput
WKUPWake-up InputInput
ICE and JTAG
TCK/SWCLKTest Clock/Serial Wire ClockInput
TDITest Data InInput
TDOTest Data OutOutput
TMS/SWDIOTest Mode Select/Serial Wire Input/OutputI/O
JTAGSELJTAG SelectionInput
Reset/Test
NRSTMicroprocessor ResetInputLow
TSTTest Mode SelectInput
NTRSTTest Reset SignalInput
Advanced Interrupt Controller - AIC
IRQExternal Interrupt InputInput
Secured Advanced Interrupt Controller - SAIC
FIQFast Interrupt InputInput
PIO Controller - PIO
PA0–PA31Parallel IO ControllerI/O
PB0–PB31Parallel IO ControllerI/O
PC0–PC31Parallel IO ControllerI/O
PD0–PD31Parallel IO ControllerI/O
External Bus Interface - EBI
D[15:0]Data BusI/O
A[25:0]Address BusOutput
NWAITExternal Wait SignalInputLow
Static Memory Controller - SMC
NCS0–NCS3Chip Select LinesOutputLow
NWR0–NWR1Write SignalOutputLow
NRDRead SignalOutputLow
NWEWrite EnableOutputLow
NBS0–NBS1Byte Mask SignalOutputLow
NANDOENAND Flash Output EnableOutputLow
NANDWENAND Flash Write EnableOutputLow
DDR2/DDR3/LPDDR1/LPDDR2/LPDDR3 Controller
DDR_CK, DDR_CLKNDDR Differential ClockOutput
DDR_CKEDDR Clock EnableOutputWhen Backup Self-refresh mode is used, should be tied to GND using 100 KΩ pull-downHigh
DDR_CSDDR Controller Chip SelectOutputLow
DDR_BA[2:0]Bank SelectOutputLow
DDR_WEDDR Write EnableOutputLow
DDR_RAS, DDR_CASRow and Column SignalOutputLow
DDR_A[13:0]DDR Address BusOutput
DDR_D[31:0]DDR Data BusI/O/-PD
DDR_DQS[3:0],

DDR_DQSN[3:0]

Differential Data StrobeI/O- PD
DDR_DQM[3:0]Write Data MaskOutput
DDR_CALDDR/LPDDR CalibrationInput
DDR_VREFDDR/LPDDR ReferenceInput
DDR_RESETNDDR3 Active Low Asynchronous ResetOutputWhen Backup Self-refresh mode is used, should be tied to VDDIODDR using 100 KΩ pull-up
Secure Data Memory Card - SDMMCx [1:0]
SDMMCx_CDSDcard / e.MMC Card DetectInput
SDMMCx_CMDSDcard / e.MMC Command lineI/O
SDMMCx_WPSDcard Connector Write Protect SignalInput
SDMMCx_RSTNe.MMC Reset SignalOutput
SDMMCx_1V8SELSDcard Signal Voltage SelectionOutput
SDMMCx_CKSDcard / e.MMC Clock SignalOutput
SDMMCx_DAT[7:0]SDcard / e.MMC Data LinesI/O
Flexible Serial Communication Controller - FLEXCOMx [4:0]
FLEXCOMx_IO0FLEXCOMx Transmit DataI/O
FLEXCOMx_IO1FLEXCOMx Receive DataI/O
FLEXCOMx_IO2FLEXCOMx Serial ClockI/O
FLEXCOMx_IO3FLEXCOMx Clear To Send / 
Peripheral Chip SelectI/O
FLEXCOMx_IO4FLEXCOMx Request To Send / 
Peripheral Chip SelectOutput
Universal Asynchronous Receiver Transmitter - UARTx [4..0]
UTXDxUARTx Transmit DataOutput
URXDxUARTx Receive DataInput
Inter-IC Sound Controller - I2SCx [1..0]
I2SCx_MCKMain System Bus ClockOutput
I2SCx_CKSerial ClockI/O
I2SCx_WSI2S Word SelectI/O
I2SCx_DI0Serial Data InputInput
I2SCx_DO0Serial Data OutputOutput
Synchronous Serial Controller - SSCx [1..0]
TDxSSC Transmit DataOutput
RDxSSC Receive DataInput
TKxSSC Transmit ClockI/O
RKxSSC Receive ClockI/O
TFxSSC Transmit Frame SyncI/O
RFxSSC Receive Frame SyncI/O
Timer/Counter - TCx [1..0]
TCLK[5..0]TC Channel y External Clock InputInput
TIOA[5..0]TC Channel y I/O Line AI/O
TIOB[5..0]TC Channel y I/O Line BI/O
Quad IO SPI - QSPIx [1..0]
QSPIx_SCKQSPI Serial ClockOutput
QSPIx_CSQSPI Chip SelectOutput
QSPIx_IO[0..3]QSPI I/O

QIO0 is QMOSI Host Out/Client In

QIO1 is QMISO Host In/Client Out

I/O
Serial Peripheral Interface - SPIx [1..0]
SPIx_MISOHost In/Client OutI/O
SPIx_MOSIHost Out/Client InI/O
SPIx_SPCKSPI Serial ClockI/O
SPIx_NPCS0SPI Peripheral Chip Select 0I/OLow
SPIx_NPCS[3..1]SPI Peripheral Chip SelectOutputLow
Two-wire Interface - TWIx [1..0]
TWDxTwo-wire Serial DataI/O
TWCKxTwo-wire Serial ClockI/O
Pulse Width Modulation Controller - PWM
PWMH0–3PWM Waveform Output HighOutput
PWML0–3PWM Waveform Output LowOutput
PWMFI0–1PWM Fault InputsInput
PWMEXTRG1–2PWM External TriggerInput
USB Host High-Speed Port - UHPHS
HHSDPAUSB Host Port A High-Speed Data +Analog
HHSDMAUSB Host Port A High-Speed Data -Analog
HHSDPBUSB Host Port B High-Speed Data +Analog
HHSDMBUSB Host Port B High-Speed Data -Analog
USB Device High-Speed Port - UDPHS
DHSDPUSB Device High-Speed Data +Analog
DHSDMUSB Device High-Speed Data -Analog
USB High-Speed Inter-Chip Port - HSIC
HHSTROBEUSB High-Speed Inter-Chip StrobeI/O
HHDATAUSB High-Speed Inter-Chip DataI/O
Ethernet 10/100 - GMAC
GREFCKReference ClockInput
GTXCKTransmit ClockInput
GRXCKReceive ClockInput
GTXENTransmit EnableOutput
GTX0–GTX3Transmit DataOutput
GTXERTransmit Coding ErrorOutput
GRXDVReceive Data ValidInput
GRX0–GRX3Receive DataInput
GRXERReceive ErrorInput
GCRSCarrier SenseInput
GCOLCollision DetectedInput
GMDCManagement Data ClockOutput
GMDIOManagement Data Input/OutputI/O
GTSUCOMPTSU timer comparison validOutput
LCD Controller - LCDC
LCDDAT[23:0]LCD Data BusOutput
LCDVSYNCLCD Vertical SynchronizationOutput
LCDHSYNCLCD Horizontal SynchronizationOutput
LCDPCKLCD Pixel ClockOutput
LCDDENLCD Data EnableOutput
LCDPWMLCDPWM for Contrast ControlOutput
LCDDISPLCD Display ON/OFFOutput
Analog-to-Digital Controller - ADC
AD0–1112 Analog InputsAnalog
ADTRGADC TriggerInput
ADVREFADC ReferenceAnalog
Security Module - SECUMOD
PIOBU0–7Tamper I/OsI/O
Image Sensor Controller - ISC
ISC_D0–ISC_D11Image Sensor DataInput
ISC_HSYNCImage Sensor Horizontal SynchroInput
ISC_VSYNCImage Sensor Vertical SynchroInput
ISC_PCKImage Sensor Pixel clockInput
ISC_MCKImage Sensor Main clockOutput
ISC_FIELDField identification signalInput
Audio Class Amplifier - CLASSD
CLASSD_L0CLASSD Left Output L0Output
CLASSD_L1CLASSD Left Output L1Output
CLASSD_L2CLASSD Left Output L2Output
CLASSD_L3CLASSD Left Output L3Output
CLASSD_R0CLASSD Right Output R0Output
CLASSD_R1CLASSD Right Output R1Output
CLASSD_R2CLASSD Right Output R2Output
CLASSD_R3CLASSD Right Output R3Output
Controller Area Network - CAN
CANRXxCAN ReceiveInput
CANTXxCAN TransmitOutput
Peripheral Touch Controller - PTC
PTC_X[7..0]X-linesOutput
PTC_Y[7..0]Y-linesInput
Pulse Density Modulation Interface Controller - PDMIC
PDMIC_DATPDM DataInput
PDMIC_CLKPDM ClockOutput