1 Peripheral Overview
The table below summarizes the feature sets of each of the timers in this document. For PIC microcontrollers, most timers will function in Sleep mode as long as the clock source remains active.
| Peripheral Name | Width | Hardware Limit(1) | Measurement | Waveform Generation | Web Links |
|---|---|---|---|---|---|
| TMR0 | 8-bit/16-bit | Yes (8-bit) | Yes | No | TMR0 |
| TMR1/3/5 | 16-bit | No | Yes | Yes (via CCP) | TMR1/3/5 |
| TMR2/4/6 | 8-bit | Yes | Yes | Yes (via CCP) | TMR2/4/6 |
| SMT | 24-bit | Yes | Yes | No | SMT |
| UTMR | Device-dependent(2) | Yes | Yes | No | UTMR |
| NCO | 16-bit/20-bit | No | No | Yes | NCO |
| CCP | 10-bit (PWM)/16-bit | No | Yes | Yes | CCP |
| PWM | 16-bit | No | No | Yes | PWM |
| WDT/WWDT | N/A | No | No | No | WDT/WWDT |
| APM | 16-bit (Base Timings)/24-bit (Offset Timings) | Yes | No | No | APM |
Note:
- Hardware limit refers to the ability to roll over at an arbitrary value rather than the maximum count possible (e.g., 0x1000 versus 0xFFFF for a 16-bit timer).
- Regarding the PIC18-Q71 family, there are two UTMR modules of 16 bits. They can be chained together to operate as a single 32-bit peripheral.