28.8 Operation Examples

Unless otherwise specified, the following notes apply to the following timing diagrams:

• Both the prescaler and postscaler are set to 1:1 (both the CKPS and OUTPS bits).
• The diagrams illustrate any clock except F_OSC/4 and show clock-sync delays of at least two full cycles for both ON and TMRx_ers. When using F_OSC/4, the clock-sync delay is at least one instruction period for TMRx_ers; ON applies in the next instruction period.
• ON and TMRx_ers are somewhat generalized, and clock-sync delays may produce results that are slightly different than illustrated.
• The PWM Duty Cycle and PWM output are illustrated assuming that the timer is used for the PWM function of the CCP module as described in the “PWM Overview” section. The signals are not a part of the Timer2 module.