11.13.20 PIR3

Peripheral Interrupt Request Register 3

Note:

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
IOCIF is a read-only bit. To clear the interrupt condition, all bits in the IOCxF registers must be cleared.
The CSWIF interrupt will not wake the system from Sleep. The system will Sleep until another interrupt causes the wake-up.

Name:	PIR3
Address:	0x46C


Bit	7	6	5	4	3	2	1	0
	TMR1GIF	TMR1IF	TMR0IF	IOCIF	VDDIO3IF	VDDIO2IF	OSFIF	CSWIF
Access	R/W/HS	R/W/HS	R/W/HS	R	R/W/HS	R/W/HS	R/W/HS	R/W/HS
Reset	0	0	0	0	0	0	0	0

Bit 7 – TMR1GIF TMR1 Gate Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 6 – TMR1IF TMR1 Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 5 – TMR0IF TMR0 Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 4 – IOCIF Interrupt-on-Change Interrupt Flag⁽²⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 3 – VDDIO3IF VDDIO3 Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 2 – VDDIO2IF VDDIO2 Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 1 – OSFIF Oscillator Failure Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 0 – CSWIF Clock Switch Interrupt Flag⁽³⁾

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. IOCIF is a read-only bit. To clear the interrupt condition, all bits in the IOCxF registers must be cleared. The CSWIF interrupt will not wake the system from Sleep. The system will Sleep until another interrupt causes the wake-up.