11.13.26 PIR9

Peripheral Interrupt Request Register 9

Note:

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
I3C2RIF is a read-only bit.
I3C2EIF is a read-only bit. To clear the interrupt condition, all bits in the I3C1ERRIRx registers must be cleared.
I3C2IF is a read-only bit. To clear the interrupt condition, all bits in the I3C1PIRx registers must be cleared.
I3C2TXIF is a read-only bit. The interrupt flag is cleared when I3CxTXB Transmit Buffer becomes full.
I3C2RXIF is a read-only bit. The interrupt flag is cleared when I3CxRXB Receive Buffer becomes empty.

Name:	PIR9
Address:	0x472


Bit	7	6	5	4	3	2	1	0
	ADTIF	ADIF	HLVDIF	I3C2RIF	I3C2EIF	I3C2IF	I3C2TXIF	I3C2RXIF
Access	R/W/HS	R/W/HS	R/W/HS	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bit 7 – ADTIF ADC Threshold Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 6 – ADIF ADC Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 5 – HLVDIF High/Low-Voltage Detect Enable Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 4 – I3C2RIF I3C2 Reset Interrupt Flag⁽²⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 3 – I3C2EIF I3C2 Error Interrupt Flag⁽³⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 2 – I3C2IF I3C2 General Interrupt Flag⁽⁴⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 1 – I3C2TXIF I3C2 Transmit Interrupt Flag⁽⁵⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 0 – I3C2RXIF I3C2 Receive Interrupt Flag⁽⁶⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. I3C2RIF is a read-only bit. I3C2EIF is a read-only bit. To clear the interrupt condition, all bits in the I3C1ERRIRx registers must be cleared. I3C2IF is a read-only bit. To clear the interrupt condition, all bits in the I3C1PIRx registers must be cleared. I3C2TXIF is a read-only bit. The interrupt flag is cleared when I3CxTXB Transmit Buffer becomes full. I3C2RXIF is a read-only bit. The interrupt flag is cleared when I3CxRXB Receive Buffer becomes empty.