11.13.23 PIR6

Peripheral Interrupt Request Register 6

Note:

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
UxIF is a read-only bit. To clear the interrupt condition, all bits in the UxUIR register must be cleared.
UxEIF is a read-only bit. To clear the interrupt condition, all bits in the UxERR register must be cleared.
UxTXIF and UxRXIF are read-only bits and cannot be set/cleared by software.

Name:	PIR6
Address:	0x46F


Bit	7	6	5	4	3	2	1	0
	U2EIF	U2IF	U2TXIF	U2RXIF	U1EIF	U1IF	U1TXIF	U1RXIF
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bit 7 – U2EIF UART2 Framing Error Interrupt Flag⁽³⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 6 – U2IF UART2 Interrupt Flag⁽²⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 5 – U2TXIF UART2 Transmit Interrupt Flag⁽⁴⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 4 – U2RXIF UART 2 Receive Interrupt Flag⁽⁴⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 3 – U1EIF UART1 Framing Error Interrupt Flag⁽³⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 2 – U1IF UART1 Interrupt Flag⁽²⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 1 – U1TXIF UART1 Transmit Interrupt Flag⁽⁴⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 0 – U1RXIF UART 1 Receive Interrupt Flag⁽⁴⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. UxIF is a read-only bit. To clear the interrupt condition, all bits in the UxUIR register must be cleared. UxEIF is a read-only bit. To clear the interrupt condition, all bits in the UxERR register must be cleared. UxTXIF and UxRXIF are read-only bits and cannot be set/cleared by software.