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14/20-Pin, Low-Power, High-Performance Microcontroller with XLP Technology

PIC18F06Q20 PIC18F16Q20

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34 UART - Universal Asynchronous Receiver Transmitter with Protocol Support
34.20 Register Definitions: UART
34.20.9 UxRXB
UxRXB

Introduction
PIC18-Q20 Family Types
Features
1 Packages
2 Pin Diagrams
3 Pin Allocation Tables
4 Guidelines for Getting Started with PIC18-Q20 Microcontrollers
5 Register and Bit Naming Conventions
6 Register Legend
7 PIC18 CPU
8 Device Configuration
9 Memory Organization
10 NVM - Nonvolatile Memory Module
11 VIC - Vectored Interrupt Controller Module
12 OSC - Oscillator Module (With Fail-Safe Clock Monitor)
13 CRC - Cyclic Redundancy Check Module with Memory Scanner
14 Resets
15 WWDT - Windowed Watchdog Timer
16 DMA - Direct Memory Access
17 Power-Saving Modes
18 PMD - Peripheral Module Disable
19 I/O Ports
20 SRPORT – Signal Routing Port
21 IOC - Interrupt-on-Change
22 PPS - Peripheral Pin Select Module
23 MVIO - Multi-Voltage I/O
24 CLC - Configurable Logic Cell
25 CLKREF - Reference Clock Output Module
26 TMR0 - Timer0 Module
27 TMR1 - Timer1 Module with Gate Control
28 TMR2 - Timer2 Module
29 UTMR - Universal Timer Module
30 CCP - Capture/Compare/PWM Module
31 Capture, Compare, and PWM Timers Selection
32 PWM - Pulse-Width Modulator with Compare
33 CWG - Complementary Waveform Generator Module
34 UART - Universal Asynchronous Receiver Transmitter with Protocol Support
35 SPI - Serial Peripheral Interface Module
36 I²C - Inter-Integrated Circuit Module
37 I3C® - Improved Inter-Integrated Circuit Module
38 HLVD - High/Low-Voltage Detect
39 FVR - Fixed Voltage Reference
40 Temperature Indicator Module
41 ADC - Analog-to-Digital Converter with Computation Module
42 Instruction Set Summary
43 ICSP™ - In-Circuit Serial Programming™
44 Register Summary
45 Electrical Specifications
46 DC and AC Characteristics Graphs and Tables
47 Packaging Information
48 Appendix A: Revision History
Microchip Information

34.20.9 UxRXB

UART Receive Register

Name:	UxRXB
Address:	0x1AF,0x1C3


Bit	7	6	5	4	3	2	1	0
	RXB[7:0]
Access	R	R	R	R	R	R	R	R
Reset	x	x	x	x	x	x	x	x

Bits 7:0 – RXB[7:0] Top of Receive FIFO

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Bits 7:0 – RXB[7:0] Top of Receive FIFO

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