7.2.2 I2C Synchronization

It is possible for the system to lose synchronization with the I/O port on the ATECC608B-TNGTLS, perhaps due to a system Reset, I/O noise or other conditions. Under this circumstance, the ATECC608B-TNGTLS may not respond as expected, may be asleep or may be transmitting data during an interval when the system is expecting to send data. To resynchronize, the following procedure can be followed:

  1. To ensure an I/O channel Reset, the system must send the standard I2C software Reset sequence as follows:
    • A Start bit condition
    • Nine cycles of SCL, with SDA held high by the system pull-up resistor
    • Another Start bit condition
    • A Stop bit condition

    It may, then, be possible to send a read sequence, and if synchronization completes properly, the ATECC608B-TNGTLS will ACK the device address. The device may return data or may leave the bus floating (which the system will interpret as a data value of 0xFF) during the data periods.

    If the device does ACK the device address, the system must reset the internal address counter to force the ATECC608B-TNGTLS to ignore any partial input command that may have been sent. This can be accomplished by sending a write sequence to word address 0x00 (Reset), followed by a Stop condition.

  2. If the device does not respond to the device address with an ACK, then it may be asleep. In this case, the system must send a complete Wake token and wait tWHI after the rising edge. The system may, then, send another read sequence, and if synchronization is complete, the device will ACK the device address.
  3. If the device still does not respond to the device address with an ACK, then it may be busy executing a command. The system must wait the longest tEXEC (max.), then send the read sequence, which will be acknowledged by the device.