29.5.4 Control D
| Name: | CTRLD |
| Offset: | 0x03 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| INITDLY[2:0] | ASDV | SAMPDLY[3:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:5 – INITDLY[2:0] Initialization Delay
This bit field defines the initialization/start-up delay before the first sample when enabling the ADC or changing to an internal reference voltage. Setting this delay will ensure that the reference, MUXes, etc., are ready before starting the first conversion. The initialization delay will also take place when waking up from deep sleep to do a measurement.
The delay is expressed several CLK_ADC cycles.
| Value | Name | Description |
|---|---|---|
| 0x0 | DLY0 | Delay 0 CLK_ADC cycles |
| 0x1 | DLY16 | Delay 16 CLK_ADC cycles |
| 0x2 | DLY32 | Delay 32 CLK_ADC cycles |
| 0x3 | DLY64 | Delay 64 CLK_ADC cycles |
| 0x4 | DLY128 | Delay 128 CLK_ADC cycles |
| 0x5 | DLY256 | Delay 256 CLK_ADC cycles |
| Other | - | Reserved |
Bit 4 – ASDV Automatic Sampling Delay Variation
Writing this bit
to ‘1’ enables automatic sampling delay variation between ADC
conversions. The purpose of varying sampling instant is to randomize the
sampling instant and thus avoid standing frequency components in the frequency
spectrum. The value of the SAMPDLY bit field is automatically incremented by one
after each sample.
0xF, it wraps around to
0x0.| Value | Name | Description |
|---|---|---|
| 0 | ASVOFF | The Automatic Sampling Delay Variation is disabled |
| 1 | ASVON | The Automatic Sampling Delay Variation is enabled |
Bits 3:0 – SAMPDLY[3:0] Sampling Delay Selection
This bit field defines the delay between consecutive ADC samples. The programmable sampling delay allows modifying the sampling frequency during hardware accumulation to suppress periodic noise sources that may otherwise disturb the sampling. The SAMPDLY bit field can also be modified automatically from one sampling cycle to another, by setting the ASDV bit. The delay is expressed as CLK_ADC cycles and is given directly by the bit field setting. The sampling cap is kept open during the delay.