25.2 I2C Mode Overview

The Inter-Integrated Circuit (I2C) bus is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A slave device is controlled through addressing. Figure 25-9 and Figure 25-10 show block diagrams of the I2C Master and Slave modes, respectively.

Figure 25-9. MSSP Block Diagram (I2C Master mode)
Figure 25-10. MSSP Block Diagram (I2C Slave mode)

The I2C bus specifies two signal connections:

  • Serial Clock (SCL)
  • Serial Data (SDA)

Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one.

Figure 25-11 shows a typical connection between two processors configured as master and slave devices.

Figure 25-11. I2C Master/Slave Connection

The I2C bus can operate with one or more master devices and one or more slave devices.

There are four potential modes of operation for a given device:

  • Master Transmit mode
 (master is transmitting data to a slave)
  • Master Receive mode
 (master is receiving data from a slave)
  • Slave Transmit mode
 (slave is transmitting data to a master)
  • Slave Receive mode
 (slave is receiving data from the master)

To begin communication, the master device transmits a Start condition followed by the address byte of the slave it intends to communicate with. A Start condition is indicated by a high-to-low transition of the SDA line while the SCL line is held high. Address and data bytes are sent out, Most Significant bit (MSb) first. This is followed by a single Read/Write Information (R/W) bit, which determines whether the master intends to transmit to or receive data from the slave device. The R/W bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave.

If the requested slave exists on the bus, it will respond with an Acknowledge sequence, otherwise known as an ACK. The Acknowledge sequence is an active-low signal, which holds the SDA line low to indicate to the transmitter that the slave device has received the transmitted data and is ready to receive more. The master then continues to either transmit to or receive data from the slave.

The transition of a data bit is always performed while the SCL line is held low. Transitions that occur while the SCL line is held high are used to indicate Start and Stop conditions.

If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding after each byte with an ACK sequence. In this example, the master device is in Master Transmit mode and the slave is in Slave Receive mode.

If the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ACK sequence. In this example, the master device is in Master Receive mode and the slave is in Slave Transmit mode.

On the last byte of data communicated, the master device may end the transmission by sending a Stop condition. If the master device is in Receive mode, it sends the Stop condition in place of the last ACK sequence. A Stop condition is indicated by a low-to-high transition of the SDA line while the SCL line is held high.

In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If so, the master device may send Restart condition in place of the Stop condition or last ACK sequence when it is in Receive mode.

The I2C bus specifies three message protocols:

  • Single message where a master writes data to a slave.
  • Single message where a master reads data from a slave.
  • Combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves.