25.1 SPI Mode Overview

The Serial Peripheral Interface (SPI) is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is selected for communication using the Slave Select feature.

The SPI bus specifies four signal connections:

  • Serial Clock (SCK)
  • Serial Data Out (SDO)
  • Serial Data In (SDI)
  • Slave Select (SS)

Figure 25-1 shows the block diagram of the MSSP module when operating in SPI mode.

Figure 25-1. MSSP Block Diagram (SPI mode)

The SPI bus operates with a single master device and one or more slave devices. When multiple slave devices are used, an independent Slave Select connection is required from the master device to each slave device. The master selects only one slave at a time. Most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected.

Figure 25-2 shows a typical connection between a master device and multiple slave devices.

Figure 25-2. SPI Master and Multiple Slave Connection

Transmissions involve two Shift registers, eight bits in size, one in the master and one in the slave. Data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register.

Figure 25-3 shows a typical connection between two processors configured as master and slave devices.

Figure 25-3. SPI Master/Slave Connection

Data is shifted out of both Shift registers on the programmed clock edge and latched on the opposite edge of the clock.

The master device transmits information out on its SDO output pin, which is connected to and received by the slave’s SDI input pin. The slave device transmits information out on its SDO output pin, which is connected to and received by the master’s SDI input pin.

To begin communication, the master device transmits both the MSb from its Shift register the clock signal. Both the master and the slave devices should be configured for the same clock polarity. During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the master device is sending out the MSb from its Shift register (on its SDO pin) and the slave device is reading this bit and saving it as the LSb of its Shift register, the slave device is also sending out the MSb from its Shift register (on its SDO pin) and the master device is reading this bit and saving it as the LSb of its Shift register.

After eight bits have been shifted out, the master and slave have exchanged register values. If there is more data to exchange, the Shift registers are loaded with new data and the process repeats itself.

Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three scenarios for data transmission:

  • Master sends useful data and slave sends dummy data.
  • Master sends useful data and slave sends useful data.
  • Master sends dummy data and slave sends useful data.

Transmissions must be performed in multiples of eight clock cycles. When there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave.

Every slave device connected to the bus that has not been selected through its slave select line must disregard the clock and transmission signals and must not transmit out any data of its own.