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Operating Conditions
- 1.9–3.6V, −40°C to +125°C, DC to
128 MHz
- AEC Q100 Grade 1 qualified
with reduced parameters
- 1.9–3.6V, −40°C to +105°C, DC to
128 MHz
- AEC Q100 Grade 2
qualified
Core: 128 MHz ARM Cortex-M4F
- 3.40 Coremark®/MHz (with IAR Compiler)
- 4 KB Combined Instruction Cache
and Data Cache
- 8-Zone Memory Protection Unit
(MPU)
- Thumb®-2
Instruction Set
- Digital Signal Processing
Application-Specific Extension (ASE) Rev 2
- Nested Vector Interrupt
Controller (NVIC)
- Embedded Trace Module (ETM) with
Instruction Trace Stream
- CoreSight™
Embedded Trace Buffer (ETB)
- Trace Port Interface Unit
(TPIU)
- IEEE 754-Compliant Single
Precision Floating Point Unit (FPU)
Memories
- 64 KB ROM for Secure Boot
- Support for asymmetric secure
boot
- 3072-Bit eFuse
- Secure boot key storage
- Debug lock
- 2 MB On-Chip Self-Programmable
Flash with:
- Error Correction Code
(ECC)
- Prefetch module to speed up
Flash accesses
- 20k cycles endurance (100k
cycles with erase retry option) and 20 years of data retention support
- 72 KB Boot Flash Memory (18
Pages, 17 Pages for Security Hash Enabled)
- 64 KB for User boot code
configuration
- 8 KB for Flexible device
configuration
- 512 KB Multi-Port Programmable
QoS SRAM Main Memory
- 256 KB of ECC RAM option
- 32 KB of RAM space for CoreSight™ ETB debug usage when enabled
- Up to 64 KB of SRAM can be
retained in Backup mode
- Up to 4 KB of Tightly Coupled
Memory (TCM)
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System
- Power-on Reset (POR) and
Brown-out Reset (BOR)
- Internal and External Clock
Options
- Integrated 16 MHz Crystal
Oscillator with ±30 ppm Stability and External Crystal Support
- External Interrupt Controller
(EIC)
- Up to four external
interrupts
- One non-maskable
interrupt
- Extensive Debug and Trace
Capabilities
- 2-Wire Serial Wire Debug
(SWD) programming and debugging interface
- ETM trace interface pins for
serial wire trace
Supported Connectivity Standards
- Bluetooth®
Low Energy SDK Qualified against Bluetooth® Core 6.0
- IEEE 802.15.4 MAC/PHY SDK for
Custom Protocol Support
- Capable of Zigbee® 3.0
- Thread 1.4
Power Supply
- System-on-chip (SoC) Uses Low
Dropout (LDO)
- Integrated PMU with:
- Buck (DC-DC/switching) mode;
supports high power (PWM), low power (PSM)
- Modular Linear Differential
Operator (MLDO) mode
- Integrated On-Chip 1.5V LDO
Regulator for eFuse
- Integrated On-Chip 1.2V Low
Dropout Regulators
- POR and BOR on 3.3V and 1.2V
Rails
- Run, Idle, Standby Sleep, Deep
Sleep and Extreme Deep Sleep Modes
- SleepWalking Peripherals
2.4 GHz RF Transceiver
- Integrated 2.4 GHz Ultra
Low-Power RF Transceiver Shared Between Bluetooth Low Energy and IEEE 802.15.4
Modems and Link (MAC) Controllers
- Integrated Transceiver (TRX)
Switch and Balun with One Single-Ended Radio Frequency Input/Output (RFIO) for
Transmit (TX)/Receive (RX)
- Hardware Radio Arbiter with
Programmable QoS:
- The resolution is up to
packet level
- Based on shared transceiver
and antenna
- High Efficiency Switching Power
Amplifier (PA)
- Programmable Transmit Output
Power Ranges from −24 dBm to +11 dBm with 1 dB Step Size
- Supported Data Rates:
- Bluetooth Low Energy 6.0: 2 Mbps, 1 Mbps, 500 kbps and 125 kbps
- IEEE 802.15.4: 250 kbps
- Proprietary 2.4 GHz: 2 Mbps,
1 Mbps and 500 kbps
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Bluetooth- Qualified against Bluetooth Core
6.0
- Up to +11 dBm Programmable
Transmit Output Power
- Typical Receiver Power
Sensitivity:
- Bluetooth Low Energy at 2
Mbps: −95 dBm
- Bluetooth Low Energy at 1
Mbps: −98 dBm
- Bluetooth Low Energy at 125
Kbps: −108 dBm
- Bluetooth Low Energy at 500
Kbps: −102 dBm
- Bluetooth Low Energy Supported
Features:
- Encrypted advertising
data
- Security level
characteristic
- Coding scheme selection
- Connection subrating
- Periodic advertising
enhancement
- Channel classification
enhancement
- Low energy power control
- 2M uncoded PHY
- Long range coded PHY
- Channel selection algorithm
#2
- Advertising extensions,
offloads CPU with hardware based scheduler
- High duty cycle
non-connectible advertising
- Data length extensions
- Secure connections
- Privacy upgrades
- Robust to interference with
wideband RSSI detector
- ECDH P256 Hardware Engine for
Bluetooth Pairing Link Key Generation
- AES128 Hardware Module for
Real-Time Bluetooth Payload Data Encryption
- Bluetooth Qualification Test
Facility (BQTF) Certification
- Supports SIG Defined/Custom
Bluetooth Low Energy Profiles and Services
- Bluetooth Low Energy Profiles:
- Bluetooth Low Energy
peripheral and central roles
- Bluetooth Low Energy APIs for
application layer to implement standard or customized GATT based
profiles/services
- Alert notification service
(Apple Notification Center Service (ANCS))
- Proximity reporter and time
information
- Multi-link and multi-role
- Bluetooth Low Energy Services:
- Provisioning
- Over-the-Air firmware update
(also known as OTA DFU)
- Advertisement/Beacon
- Personalized
configuration
- Alert notification
service
| IEEE 802.15.4 High Performance Peripherals - 16-Channel Direct Memory Access
Controller (DMAC)
- Built-in Cyclic Redundancy
Check (CRC) with memory CRC generation and monitors hardware support
- One QSPI
- Execute-In-Place (XIP)
support
- Dedicated AHB memory
zone
Low-Cost Controllerless (LCC) Graphics Solutions- Supports RGB332 8-bit color
with 480x272 TFT display
- I2C for maxTouch Control
- DMA and GPIO Pins for 8-bit
Pixel Transmission and Synchronization (1)
Cryptography - Standard AES Encryption and
Decryption with Key Sizes of 128 bits, 192 bits and 256 bits with Hardware
Accelerator
- Standard SHA Hash Algorithms,
Including SHA-256 and SHA-384 with Hardware Supported
- RSA Encryption and Decryption
with Key Sizes of 1024 bits and 2048 bits
- Elliptic Curve Digital Signature
Algorithm (ECDSA) Using All Supported NIST Curves
- NIST 800-90B Compliant True
Random Number Generator (TRNG)
- Integrated Scatter Gather
DMA
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System Peripherals- 32-Channel Event System
- All channels can be connected
to any event generator
- All channels provide a pure
asynchronous path
- Twelve channels support
synchronous and re-synchronous
- Six Serial Communication
Interfaces (SERCOM), each Configurable to Operate as:
-
Universal Synchronous Asynchronous Receiver Transmitter (USART) with full duplex and single-wire half duplex configuration
– ISO7816
– Local Interconnect Network (LIN) Commander/Responder RS485
- I2C up to 1
MHz
-
Serial Peripheral Interface (SPI)
– SPI inter-byte space
- One SERCOM Configured as
I2C-Only Interface
- Ten 16-Bit Timers/Counters (TC),
Each Configurable as:
- 16-bit TC with two
compare/capture channels
- 8-bit TC with two
compare/capture channels
- 32-bit TC with two
compare/capture channels by pairing two TCs
- Two 24-Bit Timer/Counters for
Control (TCC) with Extended Functions:
- Up to six compare channels
with optional complementary output
- Generation of synchronized
Pulse Width Modulation (PWM) pattern across port pins
- Deterministic fault
protection, fast decay and configurable dead-time between complementary
output
- Dithering to increase
resolution up to 5 bits and reduce quantization error
- One 16-Bit Timer/Counters for
Control (TCC) with Extended Functions:
- Up to two compare channels
with optional complementary output
- 34 PWM Channels: 6 Channels x 2
from 24-bit TCC, 2 Channels from 16-bit TCC, and 10 x 2 Channels from TC
- 32-Bit Real Time Counter (RTCC)
with Clock/Calendar Function
- Up to four wake-up pins with
tamper detection and debouncing filter
- Watchdog Timer (WDT) with Window
Mode
- Deadman Timer (DMT)
- Frequency Meter (FREQM)
- Configurable Custom Logic (CCL)
with Two Look-up Table (LUT)
- One 7-Bit General Purpose
Digital-to-Analog Converter (DAC)
- Two 12-Bit, up to 1 Msps
Analog-to-Digital Converter (ADC) SAR Core with up to 19 Analog Channels:
- Differential and single-ended
input
- Automatic offset and gain
error compensation
- Up to Two Analog Comparator (AC)
with Window Compare Function
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- Up to 18 Capacitive Voltage
Divider (CVD) Channels for Touch Button Support (Using Shared ADC SAR Core)
- One Temperature Sensor (Die
Temperature) Built into Wireless Subsystem
- Two Controller Area Network with
Flexible Data Rate (CAN-FD) Ports with Dedicated Direct Memory Access (DMA) and 16
Buffers, 16 Filters and 3 Masks
- ISO11898-1:2015 and CAN FD
1.0 compliant, supports up to 64 data bytes
- Arbitration bit rate up to 1
Mbps
- Data bit rate up to 10
Mbps
- Supports USB Full-Speed and
Low-Speed Compliance
- Port with up to eight
dedicated DMA channels
- Ethernet MAC (ETH)
- Compatible with IEEE Standard
802.3
- 10/100 Mbps Reduced Media
Independent Interface (RMII) with dedicated DMA
- 802.1AS and IEEE 1588-2008
Precision Time Protocol (PTP) compliant for precision clock synchronization
and TSU support
- IEEE802.3AZ/AF/PoE compliant
for energy efficiency
- Wake on Local Area Network
(LAN) support
- One Quadrature Encoder Interface
(QEI)
Oscillators
- 16 MHz, ±30 PPM Crystal/Resonator
Oscillator or External Clock (POSC) for 2.4 GHz RF Transceiver
- Shared System Phase-Locked Loop
(PLL) with RF Subsystem
- 50 MHz Ethernet Phase-Locked Loop
(EPLL)
- 96 MHz USB Phase-Locked Loop
(UPLL)
- 32.768 kHz Ultra-Low Power
Internal Oscillator (LPRC)
- Higher Accuracy 32.768 kHz, ±250
ppm Clock Options
- 32 kHz clock derived from
POSC
- 32.768 kHz crystal/resonator
oscillator (SOSC)
- External 32.768 kHz clock
source
- 8 MHz Internal RC Oscillator
(FRC)
I/O
- Peripheral Pin Select (PPS)
Support
- 23 I/Os with high-current
sink/source
- Configurable Open-Drain Output on
Digital I/O Pins
- Up to 54 Programmable I/O
Pins
DC Specification
- Electrostatic Discharge (ESD)
Protection
- Human Body Model (HBM): 2 kV
(min)
- Charged Device Model (CDM):
500V (min)
- Boot
time(2)(3): ~7.1 ms
Package- PIC32CX2501BZ62132
- 132-pin DQFN
- Size: 10 mm x 10 mm x 0.9
mm
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