16.3.3 DMA Message Size/Counters
A transaction is the transfer of one byte. A message consists of one or more transactions. A complete DMA process consists of one or more messages. The size registers determine how many transactions are in a message. The DMAnSSZ registers determine the source size and DMAnDSZ registers determine the destination size.
When a DMA transfer is initiated, the size registers are copied to corresponding counter registers that control the duration of the message. The DMAnSCNT registers count the source transactions and the DMAnDCNT registers count the destination transactions. Both are simultaneously decremented by one after each transaction.
A message is started by setting the DGO bit and terminates when the smaller of the two counters reaches zero.
When either counter reaches zero, the DGO bit is cleared and the counter and pointer registers are immediately reloaded with the corresponding size and address data. If the other counter did not reach zero, then the next message will continue with the count and address corresponding to that register. Refer to Figure 16-4.
When the Source and Destination Size registers are not equal, then the ratio of the largest to the smallest size determines how many messages are in the DMA process. For example, when the destination size is six and the source size is two, then each message will consist of two transactions and the complete DMA process will consist of three messages. When the larger size is not an even integer of the smaller size, then the last message in the process will terminate early when the larger count reaches zero. In that case, the larger counter will reset and the smaller counter will have a remainder skewing any subsequent messages by that amount.
Table 16-2 has a few examples of configuring DMA Message sizes.
1’, it is immediately reloaded from the corresponding size
register.| Operation | Example | SCNT | DCNT | Comments |
|---|---|---|---|---|
| Read from single SFR location to RAM | UART Receive Buffer | 1 | N | N equals the number of bytes desired in the destination buffer. N ≥ 1. |
| Write to single SFR location from RAM | UART Transmit Buffer | N | 1 | N equals the number of bytes desired in the source buffer. N ≥ 1. |
| Read from multiple SFR location | ADC Result registers | 2 | 2*N | N equals the number of ADC results to be stored in memory. N ≥ 1 |
| Write to Multiple SFR registers | PWM Duty Cycle registers | 2*N | 2 | N equals the number of PWM duty cycle values to be loaded from a memory table. N ≥ 1 |