7.10.1 Accessing 16-Bit Registers

Most of the registers for the ATtiny1624/1626/1627 devices are 8-bit registers, but the devices also feature a few 16-bit registers. As the AVR data bus has a width of eight bits, accessing the 16-bit requires two read or write operations. All the 16-bit registers of the ATtiny1624/1626/1627 devices are connected to the 8-bit bus through a temporary (TEMP) register.

Figure 7-3. 16-Bit Register Write Operation

For a 16-bit write operation, the low byte register (e.g., DATAL) of the 16-bit register must be written before the high byte register (e.g., DATAH). Writing the low byte register will result in a write to the temporary (TEMP) register instead of the low byte register, as shown in the left side of the figure above. When the high byte register of the 16-bit register is written, TEMP will be copied into the low byte of the 16-bit register in the same clock cycle, as shown on the right side of the same figure.

Figure 7-4. 16-Bit Register Read Operation

For a 16-bit read operation, the low byte register (e.g., DATAL) of the 16-bit register must be read before the high byte register (e.g., DATAH). When the low byte register is read, the high byte register of the 16-bit register is copied into the temporary (TEMP) register in the same clock cycle, as shown on the left side of the figure above. Reading the high byte register will result in a read from TEMP instead of the high byte register, as shown on the right side of the same figure.

The described mechanism ensures that the low and high bytes of 16-bit registers are always accessed simultaneously when reading or writing the registers.

Interrupts can corrupt the timed sequence if an interrupt is triggered during a 16-bit read/write operation, and a 16-bit register within the same peripheral is accessed in the interrupt service routine. To prevent this, interrupts should be disabled when writing or reading 16-bit registers. Alternatively, the temporary register can be read before and restored after the 16-bit access in the interrupt service routine.