25.7 Timer1 Interrupt

The TMRx register increments to FFFFh and rolls over to 0000h. When TMRx rolls over, the Timer1 interrupt flag bit of the PIRx register is set. To enable the interrupt-on-rollover, the following bits must be set:

  • The ON bit of the TxCON register
  • The TMRxIE bits of the PIEx register
  • Global interrupts must be enabled

The interrupt is cleared by clearing the TMRxIF bit as a task in the Interrupt Service Routine.

Important: The TMRx register and the TMRxIF bit must be cleared before enabling interrupts.