47.4.5 Reset, WDT, Oscillator Start-Up Timer, Power-Up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications

Figure 47-7. Reset, Watchdog Timer, Oscillator Start-Up Timer and Power-Up Timer Timing
Note:
  1. Asserted low.
Figure 47-8. Brown-out Reset Timing and Characteristics
Note:
  1. Only if the PWRTE Configuration bit is programmed to ‘1’; 2 ms delay if PWRTE = 0.
Table 47-11. 
Standard Operating Conditions (unless otherwise stated)
Param No.Sym.CharacteristicMin.Typ. †Max.UnitsConditions
RST01*TMCLRMCLR Pulse Width Low to ensure Resetμs
RST02*TIOZI/O high-impedance from Reset detection2μs
RST03TWDTWatchdog Timer Time-out Period16msWDTCPS = 00100
RST04*TPWRTPower-up Timer Period65ms
RST05TOSTOscillator Start-up Timer Period(1,2)1024TOSC
RST06VBORBrown-out Reset Voltage

2.7

2.55

2.3

1.8

2.85

2.7

2.45

1.9

3.0

2.85

2.6

2.1

V

V

V

V

BORV = 00

BORV = 01

BORV = 10

BORV = 11

RST07VBORHYSBrown-out Reset Hysteresis60mVBORV = 00
RST08TBORDCBrown-out Reset Response Time3μs
RST09VLPBORLow-Power Brown-out Reset Voltage1.81.92.2V

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note:
  1. By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency.
  2. To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended.